Design and analysis of a new loadless 4T SRAM cell in deep submicron CMOS technologies
R Sandeep, NT Deshpande… - … on Emerging Trends in …, 2009 - ieeexplore.ieee.org
The goal of this paper is to reduce the power and area of the Static Random Access Memory
(SRAM) array while maintaining the competitive performance. Here the various configuration …
(SRAM) array while maintaining the competitive performance. Here the various configuration …
Area compact 5T portless SRAM cell for high density cache in 65nm CMOS
JK Yadav, P Das, A Jain… - 2015 19th International …, 2015 - ieeexplore.ieee.org
High performance SOC contains considerable amount of SRAM memory occupying more
than 60% of total SOC area. In CMOS process scaling down of feature size enables higher …
than 60% of total SOC area. In CMOS process scaling down of feature size enables higher …
Optimization of low power 7T SRAM cell in 45nm technology
A Jain, S Sharma - 2012 Second International Conference on …, 2012 - ieeexplore.ieee.org
In this paper a low power SRAM cell is proposed. In the proposed SRAM topology,
additional circuitry has been added to a standard 6T-SRAM cell to improve the performance …
additional circuitry has been added to a standard 6T-SRAM cell to improve the performance …
Single ended 6T SRAM with isolated read-port for low-power embedded systems
This paper presents a six-transistor (6T) single-ended static random access memory (SE-
SRAM) bitcell with an isolated read-port, suitable for low-V DD and low-power embedded …
SRAM) bitcell with an isolated read-port, suitable for low-V DD and low-power embedded …
Design of 7T sram cell for low power applications
AQ Ansari, JA Ansari - 2015 Annual IEEE India Conference …, 2015 - ieeexplore.ieee.org
As the technology of memory on Systems-on-Chip (SoC) is shrinking, the compact devices
and embedded systems are emerging, so the low power consumption is very essential for …
and embedded systems are emerging, so the low power consumption is very essential for …
Single ended static random access memory for low-vdd, high-speed embedded systems
Single-ended static random access memory (SE-SRAM) is well known for their tremendous
potential of low active power and leakage dissipations. In this paper, we present a novel six …
potential of low active power and leakage dissipations. In this paper, we present a novel six …
A low leakage and SNM free SRAM cell design in deep sub micron CMOS technology
As the IC process technology scales, the oxide thickness and operating voltage continues to
decrease. The gate oxide thickness in recent and future IC process technology has …
decrease. The gate oxide thickness in recent and future IC process technology has …
Design and Implementation of 1KB SRAM array in 45 nm Technology for Low-Power Applications
AS Kumar, KN Rao, A Sujith, T Dhanuja… - 2023 3rd International …, 2023 - ieeexplore.ieee.org
Static Random Access Memory (SRAM) is a critical component of digital circuits as it is used
for high-speed data storage and retrieval. The 6T SRAM cell is a popular type of SRAM cell …
for high-speed data storage and retrieval. The 6T SRAM cell is a popular type of SRAM cell …
Design of 6T, 5T and 4T SRAM cell on various performance metrics
As the technology is shrinking, a significant amount of attention is being paid on the design
of high stability Static Random Access (SRAM) cells in terms of static Noise Margin (SNM) …
of high stability Static Random Access (SRAM) cells in terms of static Noise Margin (SNM) …
Performance evaluation of SRAM cells in 22nm predictive CMOS technology
D Hentrich, E Oruklu, J Saniie - 2009 IEEE International …, 2009 - ieeexplore.ieee.org
Static Random Access Memory (SRAM) units are often directly integrated onto the same die
with the microprocessors and influence the design metrics significantly. SRAM often …
with the microprocessors and influence the design metrics significantly. SRAM often …