Power-composition profile driven co-synthesis with power management selection for dynamic and leakage energy reduction

D Wu, BM Al-Hashimi, MT Schmitz… - … Conference on Digital …, 2005 - ieeexplore.ieee.org
Recent research has shown that the combination of dynamic voltage scaling (DVS) and
adaptive body biasing (ABB) yields high energy reductions in embedded systems …

Dynamic and Leakage Power-Composition Profile Driven Co-Synthesis for Energy and Cost Reduction

D Wu, BM Al-Hashimi, P Eles - 2004 - eprints.soton.ac.uk
Recent research has shown that combining dynamic voltage scaling (DVS) and adaptive
body bias (ABB) techniques achieve the highest reduction in embedded systems energy …

Energy-aware software development for embedded systems in HW/SW co-design

P Ehrlich, S Radke - … Symposium on Design and Diagnostics of …, 2013 - ieeexplore.ieee.org
Power constrains are becoming increasingly important for embedded systems, especially
when considering mobile applications. These systems are characterized by the presence of …

A power management methodology for high-level synthesis

G Lakshminarayana, A Raghunathan… - … Conference on VLSI …, 1998 - ieeexplore.ieee.org
In this paper, we present a power management technique targeted towards high-level
synthesis of data-dominated behavioral descriptions. Our method is founded on the …

Power-management high-level synthesis

D Macko, K Jelemenská, P Cicák - 2015 IFIP/IEEE International …, 2015 - ieeexplore.ieee.org
Power management is an integral part of almost every new system design. It enables to
keep the power under constrains, implementing such power-reduction techniques as power …

A new design partitioning approach for low power high-level synthesis

A Rettberg, FJ Rammig - Third IEEE International Workshop on …, 2006 - ieeexplore.ieee.org
The optimization of power consumption at a very high design level is a critical step towards a
power-efficient digital system design. The increasing usage of battery-powered and often …

Efficient voltage scheduling and energy-aware co-synthesis for real-time embedded systems

A Mohsen, R Hofmann - Asia-Pacific Conference on Advances in …, 2005 - Springer
This paper presents an integrated methodology and a tool for system-level low
power/energy co-synthesis for real-time embedded systems. Voltage scheduling (VS) is …

A HW/SW co-design methodology: An accurate power efficiency model and design metrics for embedded system

L Khan, TT Jeong, G Park… - 2009 10th ACIS …, 2009 - ieeexplore.ieee.org
Low-power embedded system design has become extremely important in the most recent
years. To fulfill system-level design requirements and time-to-market constraints, a power …

Integrated hardware-software co-synthesis and high-level synthesis for design of embedded systems under power and latency constraints

A Doboli - Proceedings Design, Automation and Test in Europe …, 2001 - ieeexplore.ieee.org
This paper presents an integrated approach to hardware software co-synthesis and HLS for
design of low-power embedded systems. The main motivation for this work is that fine trade …

Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

SM Martin, K Flautner, T Mudge, D Blaauw - Proceedings of the 2002 …, 2002 - dl.acm.org
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak
performance is unnecessary. However, the achievable power savings by DVS alone is …