To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit
having multiple layer wir ings and copper wirings, an address for salvaging a defect of a …

Kraus, LLP (57) ABSTRACT To reduce cost of defect redundancy and trimming in a
semiconductor integrated circuit having multiple layer wir ings and copper wirings, an …

To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit
having multiple layer wirings and copper wirings, address for salvaging defect of a memory …

An object of the present invention is to provide a semi conductor device which can solve a
problem of a layout in consideration of a high voltage application to a CMOS device. In order …

(22) Filed: Mar. 7, 2003(57) ABSTRACT (65) Prior Publication Data A Semiconductor device
has a memory cell array composed US 2004/0095830 A1 May 20, 2004 of a plurality of …

(57) ABSTRACT A semiconductor integrated circuit device has data rewrit able nonvolatile
memory cells which are formed on a semiconductor chip and in which data of three or more …

(57) ABSTRACT A Semiconductor integrated circuit device includes a memory cell array in
which a plurality of memory cells are arranged in an array, a redundant circuit which has a …

The present invention provides a method for writing data to a non-volatile Semiconductor
memory device including a plurality of memory cells which are arranged in a matrix in which …

A nonvolatile semiconductor memory with a unit cell struc ture suitable for high speed
operation and a low power supply voltage. The nonvolatile semiconductor memory includes …

Pat. No. 6,069,823, which is a continuation of application A non-volatile semiconductor
memory device comprising a N9 08/998,137, N0V~ 12, _ 1997, Pat-NO-5,920,507, which …