Row-buffer decoupling: A case for low-latency DRAM microarchitecture

O Seongil, YH Son, NS Kim… - 2014 ACM/IEEE 41st …, 2014 - ieeexplore.ieee.org
Modern DRAM devices for the main memory are structured to have multiple banks to satisfy
ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost …
被引用次数：44 相关文章

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

S Seongil, YH Son, NS Kim… - 2014 ACM/IEEE 41st …, 2014 - experts.illinois.edu
Modern DRAM devices for the main memory are structured to have multiple banks to satisfy
ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost …

Row-buffer decoupling: A case for low-latency DRAM microarchitecture

O Seongil, YH Son, NS Kim, JH Ahn - 2014 ACM/IEEE 41st International … - infona.pl
Modern DRAM devices for the main memory are structured to have multiple banks to satisfy
ever-increasing throughput, energy-efficiency, and capacity demands. Due to tight cost …