Transparent hardware management of stacked dram as part of memory
Recent technology advancements allow for the integration of large memory structures on-die
or as a die-stacked DRAM. Such structures provide higher bandwidth and faster access time …
or as a die-stacked DRAM. Such structures provide higher bandwidth and faster access time …
Cameo: A two-level memory organization with capacity of main memory and flexibility of hardware-managed cache
CC Chou, A Jaleel, MK Qureshi - 2014 47th Annual IEEE/ACM …, 2014 - ieeexplore.ieee.org
This paper analyzes the trade-offs in architecting stacked DRAM either as part of main
memory or as a hardware-managed cache. Using stacked DRAM as part of main memory …
memory or as a hardware-managed cache. Using stacked DRAM as part of main memory …
Chameleon: A dynamically reconfigurable heterogeneous memory system
Modern computing systems and applications have growing demand for memories with
higher bandwidth. This demand can be alleviated using fast, large on-die or die-stacked …
higher bandwidth. This demand can be alleviated using fast, large on-die or die-stacked …
A software-managed approach to die-stacked dram
Advances in die-stacking (3D) technology have enabled the tight integration of significant
quantities of DRAM with high-performance computation logic. How to integrate this …
quantities of DRAM with high-performance computation logic. How to integrate this …
Silc-fm: Subblocked interleaved cache-like flat memory organization
With current DRAM technology reaching its limit, emerging heterogeneous memory systems
have become attractive to continue scaling memory performance. This paper argues for …
have become attractive to continue scaling memory performance. This paper argues for …
Heterogeneous memory architectures: A HW/SW approach for mixing die-stacked and off-package memories
MR Meswani, S Blagodurov, D Roberts… - 2015 IEEE 21st …, 2015 - ieeexplore.ieee.org
Die-stacked DRAM is a technology that will soon be integrated in high-performance
systems. Recent studies have focused on hardware caching techniques to make use of the …
systems. Recent studies have focused on hardware caching techniques to make use of the …
Mempod: A clustered architecture for efficient and scalable migration in flat address space multi-level memories
A Prodromou, M Meswani, N Jayasena… - … Symposium on High …, 2017 - ieeexplore.ieee.org
In the near future, die-stacked DRAM will be increasingly present in conjunction with off-chip
memories in hybrid memory systems. Research on this subject revolves around using the …
memories in hybrid memory systems. Research on this subject revolves around using the …
The hierarchical multi-bank DRAM: A high-performance architecture for memory integrated with processors
T Yamauchi, L Hammond… - … Conference on Advanced …, 1997 - ieeexplore.ieee.org
A microprocessor integrated with DRAM on the same die has the potential to improve
system performance by reducing the memory latency and improving the memory bandwidth …
system performance by reducing the memory latency and improving the memory bandwidth …
Efficient footprint caching for tagless dram caches
Efficient cache tag management is a primary design objective for large, in-package DRAM
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …
Unison cache: A scalable and effective die-stacked DRAM cache
Recent research advocates large die-stacked DRAM caches in many core servers to break
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …