[PDF][PDF] Architectural techniques to enhance DRAM scaling

Y Kim - Ph. D. dissertation, Carnegie Mellon University, 2015 - kilthub.cmu.edu
For decades, main memory has enjoyed the continuous scaling of its physical substrate:
DRAM (DynamicRandomAccessMemory). Butnow, DRAMscalinghasreachedathreshold …

ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates

PJ Nair, DH Kim, MK Qureshi - ACM SIGARCH Computer Architecture …, 2013 - dl.acm.org
DRAM scaling has been the prime driver for increasing the capacity of main memory system
over the past three decades. Unfortunately, scaling DRAM to smaller technology nodes has …

Fine-grained activation for power reduction in DRAM

E Cooper-Balis, B Jacob - IEEE Micro, 2010 - ieeexplore.ieee.org
This DRAM architecture optimization, which appears transparent to the memory controller,
significantly reduces power consumption. With trivial additional logic, using the posted-CAS …

A case for studying DRAM issues at the system level

B Jacob - IEEE Micro, 2003 - ieeexplore.ieee.org
The widening gap between today's processor and memory speeds makes DRAM subsystem
design an increasingly important part of computer system design. If the DRAM research …

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Y Kim, R Daly, J Kim, C Fallin, JH Lee, D Lee… - ACM SIGARCH …, 2014 - dl.acm.org
Memory isolation is a key property of a reliable and secure computing system--an access to
one memory address should not have unintended side effects on data stored in other …

Reducing DRAM latency at low cost by exploiting heterogeneity

D Lee - arXiv preprint arXiv:1604.08041, 2016 - arxiv.org
In modern systems, DRAM-based main memory is significantly slower than the processor.
Consequently, processors spend a long time waiting to access data from main memory …

[PDF][PDF] Reducing DRAM latency by exploiting design-induced latency variation in modern DRAM chips

D Lee, SM Khan, L Subramanian… - CoRR abs …, 2016 - researchgate.net
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work
has studied and exploited several prior forms of this variation, such as manufacturing …

DRAM-latency optimization inspired by relationship between row-access time and refresh timing

W Shin, J Choi, J Jang, J Suh, Y Moon… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
It is widely known that relatively long DRAM latency forms a bottleneck in computing
systems. However, DRAM vendors are strongly reluctant to decrease DRAM latency due to …

Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization

KK Chang, A Kashyap, H Hassan, S Ghose… - Proceedings of the …, 2016 - dl.acm.org
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …

Scaling the" memory wall"

SL Lu, T Karnik, G Srinivasa, KY Chao… - Proceedings of the …, 2012 - dl.acm.org
DRAM has been the technology for computer main memory since Intel released the first
commercial DRAM chip (i1103) in 1970. As technology scales and demand for memory …