Based on current projections, III-Vs are expected to replace Si as the n-channel solution in
FinFETs at the 7nm technology node. The realisation of III-V FinFETs entails top-down …

The introduction of the FinFET at the 22nm technology node [1], has granted silicon (Si) an
extended stay of execution in CMOS. However, Si FinFETs are likely to scale only two …

This work describes the main challenges encountered for patterning crystalline silicon (c-Si)
fins when we scaled down the fin pitch from 124 to 90nm on a 6T-SRAM cell. The target fins …

This paper addresses the opportunities and challenges of wet and dry selective etches in
the integration of gate-all-around (GAA) field-effect transistor (FET), which is emerging as a …

As FETs are scaled, the dielectric and semiconductor channel thicknesses must be reduced
to suppress short-channel effects. Even using fin field effect transistors (finFETs) and gate all …

The first well-behaved inversion-mode InGaAs FinFET with gate length down to 100 nm with
ALD Al 2 O 3 as gate dielectric has been demonstrated. Using a damage-free sidewall …

In the deep submicron regime, FinFET successfully suppresses the leakage current using a
3D fin-like channel substrate, which gets depleted and blocks possible leakage as the gate …

FinFETs have demonstrated significant performance improvement compared to planar
devices, because of its superior short channel control and higher driving capability at a …

The junctionless MOSFET (JLFET) architecture has attracted much attention as an enabling
technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in …

InGaAs Double-gate MOSFETs with fins as narrow as 12 nm we re fabricated using
precision dry etching and digital etch. The primary goal is to use the subthreshold …