[PDF][PDF] Reducing DRAM latency by exploiting design-induced latency variation in modern DRAM chips
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work
has studied and exploited several prior forms of this variation, such as manufacturing …
has studied and exploited several prior forms of this variation, such as manufacturing …
Practical data compression for modern memory hierarchies
G Pekhimenko - arXiv preprint arXiv:1609.02067, 2016 - arxiv.org
In this thesis, we describe a new, practical approach to integrating hardware-based data
compression within the memory hierarchy, including on-chip caches, main memory, and …
compression within the memory hierarchy, including on-chip caches, main memory, and …
Rethinking memory system design
O Mutlu - 2016 Mobile System Technologies Workshop (MST), 2016 - ieeexplore.ieee.org
Summary form only given. The memory system is a fundamental performance and energy
bottleneck in almost all computing systems. Recent system design, application, and …
bottleneck in almost all computing systems. Recent system design, application, and …
Heterogeneous-Reliability Memory: Exploiting Application-Level Memory Error Tolerance
Y Luo, S Govindan, B Sharma, M Santaniello… - arXiv preprint arXiv …, 2016 - arxiv.org
This paper summarizes our work on characterizing application memory error vulnerability to
optimize datacenter cost via Heterogeneous-Reliability Memory (HRM), which was …
optimize datacenter cost via Heterogeneous-Reliability Memory (HRM), which was …
Understanding and exploiting design-induced latency variation in modern DRAM chips
Variation has been shown to exist across the cells within a modern DRAM chip. We
empirically demonstrate a new form of variation that exists within a real DRAM chip, induced …
empirically demonstrate a new form of variation that exists within a real DRAM chip, induced …
Tiered-Latency DRAM (TL-DRAM)
This paper summarizes the idea of Tiered-Latency DRAM, which was published in HPCA
2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical …
2013. The key goal of TL-DRAM is to provide low DRAM latency at low cost, a critical …
Adaptive-Latency DRAM (AL-DRAM)
This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was
published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built …
published in HPCA 2015. The key goal of AL-DRAM is to exploit the extra margin that is built …
[PDF][PDF] DRAM Bellek Gecikmelerini Azaltabilmek için Sık Kullanılan Dizelerin Yedek Dizeye Kopyalanması: Yedek Dize Yöntemi
DRAM gecikmeleri bellek işlemleri için harcanan toplam süre için önemli bir etkiye sahiptir.
Çalışmamızda önerdiğimiz yedek dize yöntemi, erişilecek hedef dizenin çoklanması ile …
Çalışmamızda önerdiğimiz yedek dize yöntemi, erişilecek hedef dizenin çoklanması ile …
Keynote: rethinking memory system design
O Mutlu - 2016 International Symposium on Rapid System …, 2016 - ieeexplore.ieee.org
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …
computing systems. Recent system design, application, and technology trends that require …
Reducing DRAM Access Latency by Exploiting DRAM Leakage Characteristics and Common Access Patterns
H Hassan - arXiv preprint arXiv:1609.07234, 2016 - arxiv.org
DRAM-based memory is a critical factor that creates a bottleneck on the system performance
since the processor speed largely outperforms the DRAM latency. In this thesis, we develop …
since the processor speed largely outperforms the DRAM latency. In this thesis, we develop …