Counter-based tree structure for row hammering mitigation in DRAM

SM Seyedzadeh, AK Jones… - IEEE Computer …, 2016 - ieeexplore.ieee.org
Scaling down DRAM technology degrades cell reliability due to increased coupling between
adjacent DRAM cells, commonly referred to as crosstalk. Moreover, high access frequency …

Architectural support for mitigating row hammering in DRAM memories

DH Kim, PJ Nair, MK Qureshi - IEEE Computer Architecture …, 2014 - ieeexplore.ieee.org
DRAM scaling has been the prime driver of increasing capacity of main memory systems.
Unfortunately, lower technology nodes worsen the cell reliability as it increases the coupling …

CoMeT: Count-Min-Sketch-based Row Tracking to Mitigate RowHammer at Low Cost

FN Bostanci, ISE Yüksel, A Olgun… - … Symposium on High …, 2024 - ieeexplore.ieee.org
DRAM chips are increasingly more vulnerable to read-disturbance phenomena (eg,
RowHammer and RowPress), where repeatedly accessing DRAM rows causes bitflips in …

HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips

AG Yağlikçi, A Olgun, M Patel, H Luo… - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …

CAT-TWO: Counter-based adaptive tree, time window optimized for DRAM row-hammer prevention

I Kang, E Lee, JH Ahn - IEEE Access, 2020 - ieeexplore.ieee.org
Row-hammering flips bits in a victim DRAM row by frequently activating its adjacent rows,
compromising DRAM integrity. Several studies propose to prevent row-hammering by …

TWiCe: Time window counter based row refresh to prevent row-hammering

E Lee, S Lee, GE Suh, JH Ahn - IEEE Computer Architecture …, 2017 - ieeexplore.ieee.org
Computer systems using DRAM are exposed to row-hammering attacks, which can flip data
in a DRAM row without directly accessing a row but by frequently activating its adjacent …

Mitigating wordline crosstalk using adaptive trees of counters

SM Seyedzadeh, AK Jones… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
DRAM technology scaling has the undesirable side effect of degrading cell reliability. One
such concern of deeply scaled DRAMs is the increased coupling between adjacent cells …

Revisiting rowhammer: An experimental analysis of modern dram devices and mitigation techniques

JS Kim, M Patel, AG Yağlıkçı, H Hassan… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
RowHammer is a circuit-level DRAM vulnerability, first rigorously analyzed and introduced in
2014, where repeatedly accessing data in a DRAM row can cause bit flips in nearby rows …

Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows

AG Yağlikçi, M Patel, JS Kim, R Azizi… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Aggressive memory density scaling causes modern DRAM devices to suffer from
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …

Hydra: Enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking

M Qureshi, A Rohan, G Saileshwar… - Proceedings of the 49th …, 2022 - dl.acm.org
DRAM systems continue to be plagued by the Row-Hammer (RH) security vulnerability. The
threshold number of row activations (TRH) required to induce RH has reduced rapidly from …