A High Data Rate Swing Enhanced CMOS Pulse Generator with an Overhead Reducing Technique
A high data rate CMOS pulse generator employing an overhead reducing technique for
wireless interconnect applications is designed in 90 nm CMOS technology. A maximum data …
wireless interconnect applications is designed in 90 nm CMOS technology. A maximum data …
Analysis and implementation of quick-start pulse generator by CMOS flipped on quartz substrate
P Kanjanavirojkul, NN Mai-Khanh… - 2016 IEEE radio …, 2016 - ieeexplore.ieee.org
This paper presents a pulse generator (PG), aiming at low power applications with low duty
cycle. The PG is capable to provide an efficient pulse generation at a frequency near and …
cycle. The PG is capable to provide an efficient pulse generation at a frequency near and …
A cmos short pulse generator with a high-voltage stacked mosfet switch
J Sun, P Wang - … Midwest Symposium on Circuits and Systems …, 2014 - ieeexplore.ieee.org
This paper presents a CMOS short pulse generator with a high-voltage stacked MOSFET
switch, which is developed to overcome the low breakdown voltage limitations of CMOS …
switch, which is developed to overcome the low breakdown voltage limitations of CMOS …
Fully integrated high voltage pulse driver using switched-capacitor voltage multiplier and synchronous charge compensation in 65-nm CMOS
This brief presents a high efficiency fully integrated high-voltage (HV) pulse driver in
standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system …
standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system …
[PDF][PDF] Implementation of an Economical and Compact Single MOSFET High Voltage Pulse Generator
S Krishnaveni, V Rajini - Indian Journal of Science and …, 2015 - researchgate.net
The high voltage load applications need very compact generators for the production of fast
rising high voltage pulses and are invited in many applications including plasma soft X-ray …
rising high voltage pulses and are invited in many applications including plasma soft X-ray …
High speed cmos pulse generator based on analog ramp signal implemented in 65nm cmos process technology
CTC Doloriel, AB Caberos - 2019 19th International …, 2019 - ieeexplore.ieee.org
A Low frequency signal cannot provide desired system specifications and causes
unsteadiness to an electronic system. To cope up with the modern signal generation, a …
unsteadiness to an electronic system. To cope up with the modern signal generation, a …
Low power ultra-wide band pulse generator based on a duty-cycled 2-ask emitter
FA Schoulten, AA Mariano, R Vauche… - 2021 19th IEEE …, 2021 - ieeexplore.ieee.org
This paper presents an ultra-wideband pulse generator based on a duty-cycled 2-ASK
emitter able to generate OOK and BPSK modulated carriers. This emitter uses a differential …
emitter able to generate OOK and BPSK modulated carriers. This emitter uses a differential …
Impulse signal generator based on current-mode excitation and transmission line resonator
P Kanjanavirojkul, NN Mai-Khanh… - 2017 15th IEEE …, 2017 - ieeexplore.ieee.org
This paper reports a novel wideband pulse generator implemented in CMOS flipped on a
quartz substrate, for low power and low duty cycle applications. The proposed circuit is …
quartz substrate, for low power and low duty cycle applications. The proposed circuit is …
A 3.1–6.65 GHz, 933µW impulse radio pulse generator with tuneable spectrum in 0.18 µm CMOS
JB Radic, AM Djugova, LF Nagy… - 2013 11th International …, 2013 - ieeexplore.ieee.org
A low-power tuneable impulse radio ultra wide band (IR-UWB) pulse generator (PG) for 3.1-
6.65 GHz band applications is proposed. To provide compensation due to process, voltage …
6.65 GHz band applications is proposed. To provide compensation due to process, voltage …
All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS
A reconfigurable, 3-50GHz all-digital impulse generator for short-distance wireless
communications is designed in 40nm-CMOS. Digital back-gate biasing is used for raised …
communications is designed in 40nm-CMOS. Digital back-gate biasing is used for raised …