Optimization of structure and electrical characteristics for four-layer vertically-stacked horizontal gate-all-around Si nanosheets devices

Q Zhang, J Gu, R Xu, L Cao, J Li, Z Wu, G Wang, J Yao… - Nanomaterials, 2021 - mdpi.com
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si
nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release …

Fabrication and characterization of stacked poly-Si nanosheet with gate-all-around and multi-gate junctionless field effect transistors

MJ Tsai, KH Peng, CJ Sun, SC Yan… - IEEE Journal of the …, 2019 - ieeexplore.ieee.org
Present work demonstrates the vertically double stacked nanosheet (NS) p-channel
polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate …

[PDF][PDF] Scaled, novel effective workfunction metal gate stacks for advanced low-V T, gate-all-around vertically stacked nanosheet FETs with reduced vertical distance …

A Veloso, E Simoen, A Oliveira, A Chasin… - … Conference on Solid …, 2019 - researchgate.net
We report on gate-all-around (GAA) vertically stacked lateral silicon nanosheet (NS) FETs as
promising candidates to deliver a better power-performance metric for advanced logic …

A comprehensive investigation of vertically stacked silicon nanosheet field effect transistors: an analog/rf perspective

S Tayal, J Ajayan, LMIL Joseph, J Tarunkumar… - Silicon, 2022 - Springer
In this article, the analog/RF performance of n-channel vertically stacked gate all around
(GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D …

Design study of the gate-all-around silicon nanosheet MOSFETs

Y Lee, GH Park, B Choi, J Yoon, HJ Kim… - Semiconductor …, 2020 - iopscience.iop.org
The gate-all-around (GAA) silicon nanosheet (SiNS) metal-oxide-semiconductor field-effect
transistor (MOSFET) structures have been recognized as excellent candidates to achieve …

Stacked SiGe nanosheets p-FET for Sub-3 nm logic applications

CL Chu, SH Hsu, WY Chang, GL Luo, SH Chen - Scientific Reports, 2023 - nature.com
The fabrication of vertically stacked SiGe nanosheet (NS) field-effect transistors (FETs) was
demonstrated in this study. The key process technologies involved in this device fabrication …

4-levels vertically stacked sige channel nanowires gate-all-around transistor with novel channel releasing and source and drain silicide process

X Cheng, Y Li, F Zhao, A Chen, H Liu, C Li, Q Zhang… - Nanomaterials, 2022 - mdpi.com
In this paper, the fabrication and electrical performance optimization of a four-levels
vertically stacked Si0. 7Ge0. 3 channel nanowires gate-all-around transistor are explored in …

Hybrid integrated Si nanosheet GAA-FET and stacked SiGe/Si FinFET using selective channel release strategy

F Zhao, X Jia, H Luo, J Zhang, XT Mao, Y Li… - Microelectronic …, 2023 - Elsevier
A hybrid integration scheme of Si nanosheet (NS) gate-all-around (GAA) field-effect
transistor (FET) and stacked SiGe/Si FinFET is explored in detail. Si NS GAA-FET can …

Characteristics of stacked gate-all-around Si nanosheet MOSFETs with metal sidewall source/drain and their impacts on CMOS circuit properties

WL Sung, Y Li - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
In this brief, we computationally examine electrical characteristics of stacked gate-all-around
Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) …

Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process

Y Zhang, X Ai, X Yin, H Zhu, H Yang… - … on Electron Devices, 2021 - ieeexplore.ieee.org
We presented and demonstrated a new type of vertical nanowire (NW) and nanosheet (NS)
field-effect transistors (FETs), named vertical sandwich gate-all-around FETs or VSAFETs …