Leakage optimization of the buried oxide substrate of nanosheet field-effect transistors

S Yoo, S Kim - IEEE Transactions on Electron Devices, 2022 - ieeexplore.ieee.org
In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is
proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet …

Trench gate nanosheet FET to suppress leakage current from substrate parasitic channel

KS Lee, BD Yang, JY Park - IEEE Transactions on Electron …, 2023 - ieeexplore.ieee.org
Recently, nanosheet FETs (NS FETs) have been introduced as promising candidates for
beyond 3-nm node technology. However, difficulties remain for mass production of the NS …

Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

S Lee, J Jeong, S Lee, J Lee, J Lim… - … on Electron Devices, 2023 - ieeexplore.ieee.org
The optimal inner spacer length () for each layer in nanosheet (NS) field-effect transistors
(FETs) was investigated using a technology computer-aided design (TCAD) simulation …

Optimized substrate for improved performance of stacked nanosheet field-effect transistor

V Jegadheesan, K Sivasankaran… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered
as a promising candidate for continued scaling with silicon. While using punchthrough …

Proposal and investigation of area scaled nanosheet tunnel FET: A physical insight

S Srivastava, S Panwar… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
While considering the low power demand as a fundamental bottleneck for nanoscale
devices, this work comprehensively investigates a novel concept that incorporates the area …

Novel trench inner-spacer scheme to eliminate parasitic bottom transistors in silicon nanosheet FETs

J Jeong, JS Yoon, S Lee… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic
bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors …

A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors

V Jegadheesan, K Sivasankaran - Journal of Computational Electronics, 2020 - Springer
For continued scaling with silicon, the stacked nanosheet field-effect transistor (SNSH-FET)
is considered to be a major candidate for sub-7-nm technology. The radiofrequency …

Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain

JS Yoon, J Jeong, S Lee, RH Baek - IEEE Access, 2019 - ieeexplore.ieee.org
Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively
analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the …

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

Y Choi, K Lee, KY Kim, S Kim, J Lee, R Lee… - Solid-State …, 2020 - Elsevier
By using technology computer aided design (TCAD) simulation, the aim of this paper is to
investigate the effect of Si parasitic channel, which is placed under stacked nanosheet …

Impact of device-to-device interference in nanosheet field-effect transistors

KS Lee, WC Shin, JW Yeon, JY Park - Microelectronics Reliability, 2023 - Elsevier
Nanosheet field-effect transistors (NS FETs) are a promising candidate for extremely scaled
logic devices beyond FinFETs. The benefits of NS FETs include superior design flexibility …