N-type nanosheet FETs without ground plane region for process simplification

KS Lee, JY Park - Micromachines, 2022 - mdpi.com
This paper proposes a simplified fabrication processing for nanosheet Field-Effect
Transistors (FETs) part of beyond-3-nm node technology. Formation of the ground plane …

A review of the gate-all-around nanosheet FET process opportunities

S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …

NS3K: A 3-nm nanosheet FET standard cell library development and its impact

T Kim, J Jeong, S Woo, J Yang, H Kim… - … Transactions on Very …, 2022 - ieeexplore.ieee.org
Nanosheet FETs (NSFETs) are attracting attention as promising devices that can replace
FinFETs beyond the 5-nm node. Despite the importance of the devices, few studies analyze …

Nanosheet FETs at 3 nm

S Thomas - Nature electronics, 2018 - nature.com
Improved functionality and performance in integrated circuits has principally been achieved
by shrinking transistors and squeezing more of them onto each square inch of silicon. As …

(Invited) Epitaxy of (SiGe/Si) Superlattices for the Fabrication of Horizontal Gate-All-Around Nanosheet Transistors

NJ Loubet, J Li, R Chao, C Yeung… - Electrochemical …, 2018 - iopscience.iop.org
Stacked horizontal Gate All Around Nanosheet transistors were recently proposed as a
replacement of FinFET for the sub-7nm device nodes. In order to stack Nanosheet channels …

[HTML][HTML] Hierarchical simulation of nanosheet field effect transistor: NESS flow

D Nagy, A Rezaei, N Xeni, T Dutta, F Adamu-Lema… - Solid-State …, 2023 - Elsevier
Nanosheet gate-all-around transistor devices have been an important contenders for future
technology nodes. Compared to FinFETs they have superior electrostatic control. The …

Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain

JS Yoon, J Jeong, S Lee, RH Baek - IEEE Access, 2019 - ieeexplore.ieee.org
Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively
analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the …

Novel Scheme of Inner Spacer Length Optimization for Sub-3-nm Node Silicon n/p Nanosheet Field-Effect Transistors

S Lee, J Jeong, S Lee, J Lee, J Lim… - … on Electron Devices, 2023 - ieeexplore.ieee.org
The optimal inner spacer length () for each layer in nanosheet (NS) field-effect transistors
(FETs) was investigated using a technology computer-aided design (TCAD) simulation …

Vertical n-type and p-type nanosheet FETs with C-shaped channel

ZR Xiao, HL Zhu, Q Wang, Z Chen… - … on Electron Devices, 2023 - ieeexplore.ieee.org
We presented and demonstrated both n-and p-type vertical C-shaped-channel nanosheet
field-effect transistors (VCNFETs) featured with precise control of both channel thickness …

A source/drain-on-insulator structure to improve the performance of stacked nanosheet field-effect transistors

V Jegadheesan, K Sivasankaran - Journal of Computational Electronics, 2020 - Springer
For continued scaling with silicon, the stacked nanosheet field-effect transistor (SNSH-FET)
is considered to be a major candidate for sub-7-nm technology. The radiofrequency …