Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation
V Chauhan, DP Samajdar - Journal of Physics D: Applied Physics, 2023 - iopscience.iop.org
Negative-capacitance fin field-effect transistors (NC-FinFETs), due to their superior gate
electrostatics and dominance over short channel effects (SCEs), have been a key …
electrostatics and dominance over short channel effects (SCEs), have been a key …
Spectral interferometry for fully integrated device metrology
A spectral interferometry technique called vertical travelling scatterometry (VTS) is
introduced, demonstrated, and discussed. VTS utilizes unique information from spectral …
introduced, demonstrated, and discussed. VTS utilizes unique information from spectral …
Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications
K Chen, J Yang, C Wu, C Wang, M Xu… - IEEE Access, 2023 - ieeexplore.ieee.org
The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs
This study proposed a novel source/drain (S/D) extension scheme to increase the stress in
nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using …
nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using …
Reliability challenges in Forksheet Devices
E Bury, M Vandemaele, J Franco… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
The forksheet (FSH) device architecture is a possible candidate towards continued logic cell
downscaling. It consists of vertically stacked n-and p-type sheets at opposing sides of a …
downscaling. It consists of vertically stacked n-and p-type sheets at opposing sides of a …
Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits
SR Kola, Y Li - 2023 - preprints.org
In this paper, we study the effect of parasitic channel on electrical characteristics and power
consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs …
consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs …
Leakage Reduction of GAA Stacked SI Nanosheet CMOS Transistors and 6T-SRAM Cell Via Spacer Bottom Footing Optimization
J Yao, X Zhang, L Cao, J Li, N Zhou, Q Li… - 2023 China …, 2023 - ieeexplore.ieee.org
In this work, the significant leakage reduction approach is proposed and investigated by
critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si …
critical spacer bottom footing (SBF) optimization for gate-all-around (GAA) stacked Si …
Design and Investigation of Stacked Nanosheet Transistor Parameters for Analog Performance
VK Kakar, PK Pal - 2023 International Conference on Device …, 2023 - ieeexplore.ieee.org
The work proposes a characteristic analysis of nanosheet MOSFET and also analyzed on
the basis of analog application performance. A substack design for better AF performance is …
the basis of analog application performance. A substack design for better AF performance is …
Gate-all-around devices with isolated and non-isolated epitaxy regions for strain engineering
AM Greene, J Frougier, J Zhang, SD Suk… - US Patent …, 2023 - Google Patents
2021-03-26 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …