Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …

Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor

S Rathore, RK Jaisawal, N Gandhi, PN Kondekar… - Microelectronics …, 2022 - Elsevier
The continued scaling of 3D transistors into the ultra-scaled-down nanoscale regime causes
self-heating effect (SHE) driven thermal deterioration. Particularly in silicon-on-insulator …

Investigation of ambient temperature and thermal contact resistance induced self-heating effects in nanosheet FET

S Rathore, RK Jaisawal, P Suryavanshi… - Semiconductor …, 2022 - iopscience.iop.org
Self-heating effect (SHE) is a severe issue in advanced nano-scaled devices such as
stacked nanosheet field-effect transistors (NS-FET), which raises the device temperature …

Investigation of Analog/RF and linearity performance with self-heating effect in nanosheet FET

S Rathore, RK Jaisawal, PN Kondekar, N Bagga - Microelectronics Journal, 2023 - Elsevier
In vertically stacked gate-all-around Nanosheet FET (NSFET), the channels/sheets are
wrapped by a low thermal conductivity material, which hinders the active heat flow path and …

Design optimization of three-stacked nanosheet FET from self-heating effects perspective

S Rathore, RK Jaisawal, PN Kondekar… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Self-heating effect (SHE) is a severe issue arising in the nanoscale field-effect transistors
(FETs). It raises the device's lattice temperature several degrees higher than the ambient …

Hetero-interfacial thermal resistance effects on device performance of stacked gate-all-around nanosheet FET

S Venkateswarlu, K Nayak - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon
scattering and weak electron-phonon coupling at hetero-interfaces, can impact stacked Si …

Electro-thermal performance boosting in stacked Si gate-all-around nanosheet FET with engineered source/drain contacts

S Venkateswarlu, O Badami… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-
around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) …

Layout design correlated with self-heating effect in stacked nanosheet transistors

L Cai, W Chen, G Du, X Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
With technology node scaling down to 5 nm, the narrow device geometry confines the
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …

Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options

C Yoo, J Chang, Y Seon, H Kim… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Self-heating effects (SHEs) of multi-nanosheet FET (mNS-FET) at the 3-nm technology node
were analyzed at the device and circuit level considering the introduction of punchthrough …

A physics-based thermal model of nanosheet MOSFETs for device-circuit co-design

L Cai, W Chen, P Chang, G Du, X Zhang… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
A physics-based thermal model is developed to describe the self-heating effects (SHE) on
nanosheet MOSFETs. Three stages of transient temperature response due to the anisotropic …