Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications
K Chen, J Yang, C Wu, C Wang, M Xu… - IEEE Access, 2023 - ieeexplore.ieee.org
The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
(GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically …
Gate-All-Around Strained Si0.4Ge0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application
A Agrawal, S Chouksey, W Rachmady… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
For the first time, we report a short channel high performance, gate-all-around strained Si 0.4
Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate …
Ge 0.6 nanosheet PMOSFET with aggressively scaled dimensions. We demonstrate …
Performance analysis of Si-channel nanosheet FETs with strained SiGe source/drain stressors
Abstract Silicon channel Nanosheet Field Effect Transistors (NSFETs) are integrated with
diamond-shaped embedded-Si 1− x Ge x source/drain (S/D) stressors to boost the electrical …
diamond-shaped embedded-Si 1− x Ge x source/drain (S/D) stressors to boost the electrical …
Advantage of NW structure in preservation of SRB-induced strain and investigation of off-state leakage in strained stacked Ge NW pFET
H Arimura, G Eneman, E Capogreco… - 2018 IEEE …, 2018 - ieeexplore.ieee.org
Nanowires (NW) and nanosheets (NS) are promising channel structure for future technology
nodes as they can offer better electrostatics than FinFETs. In this paper, we show another …
nodes as they can offer better electrostatics than FinFETs. In this paper, we show another …
Compressive Strained Si1-XGex Channel for High Performance Gate-All-Around Nanosheet Transistors
S Mochizuki, J Li, E Stuckert, H Zhou… - … Meeting Abstracts 242, 2022 - iopscience.iop.org
As scaling of conventional FinFET architecture to achieve target transistor density and
performance becomes more complex and difficult, it is essential to attain a next generation …
performance becomes more complex and difficult, it is essential to attain a next generation …
Novel postgate single diffusion break integration in gate-all-around nanosheet transistors to achieve remarkable channel stress for N/P current matching
T Liu, D Wang, Z Pan, K Chen, J Yang… - … on Electron Devices, 2022 - ieeexplore.ieee.org
A novel integration scheme of postgate single diffusion break (PG-SDB) has been proposed
to enhance channel stress for Si gate-all-around (GAA) nanosheet field-effect transistors (NS …
to enhance channel stress for Si gate-all-around (GAA) nanosheet field-effect transistors (NS …
Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel
S Mochizuki, M Bhuiyan, H Zhou… - 2020 IEEE …, 2020 - ieeexplore.ieee.org
Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si 1-x Ge x
channel have been fabricated to explore their electrical benefits. The Si 1-x Ge x NS channel …
channel have been fabricated to explore their electrical benefits. The Si 1-x Ge x NS channel …
Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers
C Li, Y Shao, F Kuang, F Liu, Y Wang, X Li, Y Zhuang - Micromachines, 2024 - mdpi.com
In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the
gate, with SiC layers under the source and drain, to improve the leakage current and thermal …
gate, with SiC layers under the source and drain, to improve the leakage current and thermal …
Nanoscale CMOSFET performance improvement and reliability study for local strain techniques
HL Huang, JK Chen, MP Houng - Solid-state electronics, 2013 - Elsevier
In this paper, we report the investigation on a nanoscale complementary metal–oxide–
semiconductor field-effect transistor (CMOSFET) fabricated by local strained channel …
semiconductor field-effect transistor (CMOSFET) fabricated by local strained channel …
The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs
OM Alatise, KSK Kwa, SH Olsen, AG O'Neill - Solid-State Electronics, 2010 - Elsevier
The impact of the thickness of the silicon–germanium strain-relaxed buffer (SiGe SRB) on
the analog performance of strained Si nMOSFETs is investigated. The negative drain …
the analog performance of strained Si nMOSFETs is investigated. The negative drain …