Modern architectures rely on memory fences to prevent undesired weakenings of memory
consistency. As the fences' semantics may be subtle, the automation of their placement is …

The emergence of new architectures create a recurring challenge to ensure that existing
programs still work on them. Manually porting legacy code is often impractical. Static binary …

We present an algorithm for automatically checking robustness of concurrent programs
against C/C++ 11 release/acquire semantics, namely verifying that all program behaviors …

We propose an under-approximate reachability analysis algorithm for programs running
under the POWER memory model, in the spirit of the work on context-bounded analysis …

We study the problem of verifying the robustness of concurrent programs against a C11-style
memory model that includes relaxed accesses and release/acquire accesses and fences …

Dynamic Binary Translation (DBT) is a powerful approach to support cross-architecture
emulation of unmodified binaries. However, DBT systems face correctness and performance …

We address the problem of verifying safety properties of concurrent programs running over
the Total Store Order (TSO) memory model. Known decision procedures for this model are …

We address the problem of verifying safety properties of concurrent programs running over
the TSO memory model. Known decision procedures for this model are based on complex …

The full semantics of the Intel-x86 architecture has been defined by Raad et al in POPL
2022, extending the earlier formalization based on the TSO memory model incorporating …

Modern architectures provide weaker memory consistency guarantees than sequential
consistency. These weaker guarantees allow programs to exhibit behaviours where the …