A new high-speed and low area efficient pipelined 128-bit adder based on modified carry look-ahead merging with Han-Carlson tree method
In this paper, a 128-bit pipeline Adder is presented, in the form of a syntactic Tree Adder by
an introduction of a new modified Carry-Look-Ahead (CLA) that is merged inside the Tree …
an introduction of a new modified Carry-Look-Ahead (CLA) that is merged inside the Tree …
Low power and highly reliable 8-bit carry select adder
Pritty, M Jhamb - Innovations in Electrical and Electronic Engineering …, 2021 - Springer
In today's enhanced technological advancements, a carry select adder performs an
indispensable integral part of the complex processing of data. It exhibits promising results in …
indispensable integral part of the complex processing of data. It exhibits promising results in …
Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination
A Ravindran, A George, AM George… - … on Recent Advances …, 2023 - ieeexplore.ieee.org
This paper analyses the performance of different adders in terms of power delay and area.
Adders are fundamental units in arithmetic circuits. Adders, till now, have undergone several …
Adders are fundamental units in arithmetic circuits. Adders, till now, have undergone several …
Single bit hybrid full adder cell by gate diffusion input and pass transistor logic technique
R Goyal, S Sharma - … on Advances in Electrical Technology for …, 2017 - ieeexplore.ieee.org
In this paper, single bit full adder hybrid circuit has been proposed which consist of two
techniques ie Pass transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic …
techniques ie Pass transistor Logic (PTL) and Gate Diffusion Technique (GDI). Several logic …
32 bit power efficient carry select adder using 4T XNOR gate
SB Rashmi, V Oli - … on Applied and Theoretical Computing and …, 2016 - ieeexplore.ieee.org
Adders are the basic elements used in complex data processing for efficient VLSI design.
The CSLA adder circuit is used for the design of high speed processors. There is scope for …
The CSLA adder circuit is used for the design of high speed processors. There is scope for …
[PDF][PDF] REDUCTION IN AREA AND POWER ANALYSIS WITH D-LATCH ENABLED CARRY SELECT ADDER USING GATE DIFFUSION INPUT
S BHATNAGAR, V AGRAWAL - academia.edu
Arithmetic operation addition is the most frequently used in micro-processors, signal
processors of digital computers. It acts as a back bone for the combination of other arithmetic …
processors of digital computers. It acts as a back bone for the combination of other arithmetic …
[PDF][PDF] A REVIEW PAPER ON HIGH PERFORMANCE 1-BIT FULL ADDERS DESIGN AT 90NM TECHNOLOGY
NL Reddy, M Bassi, S Verma - researchgate.net
This paper provides a comparative analysis of various full adders in terms of power, delay
and PDP. From the survey of literature, conventional 28T full adder, SERF 10T full adder …
and PDP. From the survey of literature, conventional 28T full adder, SERF 10T full adder …
For Enhancing the Performance in Single Bit Hybrid Full Adder Circuits Using XNOR Gate
E Jadon, S Akashe - … International Conference, CNC 2020, Gwalior, India …, 2021 - Springer
In this paper, the use of XNOR Gate was proposed for single-bit full adder hybrid circuits.
Performance of single-bit full Adder hybrid circuits is completely determined by their key …
Performance of single-bit full Adder hybrid circuits is completely determined by their key …
Analysis of MOSFET density and reduction in power consumption of Carry Select Adder using gate diffusion input
S Bhatnagar, V Agrawal… - … Conference on Recent …, 2016 - ieeexplore.ieee.org
The level of integration keeps on emerging which results in more and more complicated
signal processors to be incorporated on a single chip. The applications of signal processing …
signal processors to be incorporated on a single chip. The applications of signal processing …