Towards acceleration of fault simulation using graphics processing units

K Gulati, SP Khatri - Proceedings of the 45th Annual Design Automation …, 2008 - dl.acm.org
In this paper, we explore the implementation of fault simulation on a Graphics Processing
Unit (GPU). In particular, we implement a fault simulator that exploits thread level …

Efficient fault simulation on many-core processors

MA Kochte, M Schaal, HJ Wunderlich… - Proceedings of the 47th …, 2010 - dl.acm.org
Fault simulation is essential in test generation, design for test and reliability assessment of
integrated circuits. Reliability analysis and the simulation of self-test structures are …

Sequential circuit fault simulation using logic emulation

SA Hwang, JH Hong, CW Wu - IEEE Transactions on Computer …, 1998 - ieeexplore.ieee.org
A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit
configured into our system that emulates the faulty circuit's behaviour is synthesized from the …

An evaluation of parallel simulated annealing strategies with application to standard cell placement

JA Chandy, S Kim, B Ramkumar… - … on Computer-Aided …, 1997 - ieeexplore.ieee.org
Simulated annealing, a methodology for solving combinatorial optimization problems, is a
very computationally expensive algorithm and, as such, numerous researchers have …

Data parallel fault simulation

MB Amin, B Vinnakota - IEEE transactions on very large scale …, 1999 - ieeexplore.ieee.org
Fault simulation is a computer-intensive problem. Parallel processing is one method to
reduce simulation time. In this paper, we discuss a technique to partition the fault set for fault …

3-D parallel fault simulation with GPGPU

M Li, MS Hsiao - … Transactions on Computer-Aided Design of …, 2011 - ieeexplore.ieee.org
General purpose computing on graphical processing units (GPGPU) is a paradigm shift in
computing that promises a dramatic increase in performance. GPGPU also brings an …

[PDF][PDF] Генетические алгоритмы построения входных идентифицирующих последовательностей цифровых устройств

ДЕ Иванов - Донецк: ТОВ «Цифровая типографiя, 2012 - researchgate.net
Цифровая техника нашла широкое применение как в производстве, так и в быту. В
обеих сферах применения потребитель вправе требовать высокой надёжности …

Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System

J Hu, G Dai, L Wang, L Lai, Y Huang… - … on Computer-Aided …, 2022 - ieeexplore.ieee.org
Fault simulation is a critical component of the automatic test pattern generation (ATPG) tool,
which is widely used in chip development. The CPU–GPU heterogeneous system can …

Fault table computation on GPUs

K Gulati, SP Khatri - Journal of Electronic Testing, 2010 - Springer
In this paper, we explore the implementation of fault table generation on a Graphics
Processing Unit (GPU). A fault table is essential for fault diagnosis and fault detection in …

Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count

R Butler, B Keller, S Paliwal… - … 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
We present an implementation for parallel ATPG that is constructed so as to achieve a test
vector count comparable to the serial algorithm. This task posed a challenge since, unlike …