High-level synthesis design space exploration: Past, present, and future

BC Schafer, Z Wang - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
This article presents a survey of the different modern high-level synthesis (HLS) design
space exploration (DSE) techniques that have been proposed so far to automatically …

On learning-based methods for design-space exploration with high-level synthesis

HY Liu, LP Carloni - Proceedings of the 50th annual design automation …, 2013 - dl.acm.org
This paper makes several contributions to address the challenge of supervising HLS tools
for design space exploration (DSE). We present a study on the application of learning-based …

Active learning for multi-objective optimization

M Zuluaga, G Sergent, A Krause… - … on machine learning, 2013 - proceedings.mlr.press
In many fields one encounters the challenge of identifying, out of a pool of possible designs,
those that simultaneously optimize multiple objectives. This means that usually there is not …

[HTML][HTML] Multi-objective design of aircraft maintenance using Gaussian process learning and adaptive sampling

J Lee, M Mitici - Reliability Engineering & System Safety, 2022 - Elsevier
Aircraft maintenance design aims to identify strategies that render the aircraft reliable for
flight in a cost-efficient manner. These are often conflicting objectives. Moreover, existing …

e-pal: An active learning approach to the multi-objective optimization problem

M Zuluaga, A Krause - Journal of Machine Learning Research, 2016 - jmlr.org
In many fields one encounters the challenge of identifying out of a pool of possible designs
those that simultaneously optimize multiple objectives. In many applications an exhaustive …

Neural networks designing neural networks: multi-objective hyper-parameter optimization

SC Smithson, G Yang, WJ Gross… - 2016 IEEE/ACM …, 2016 - ieeexplore.ieee.org
Artificial neural networks have gone through a recent rise in popularity, achieving state-of-
the-art results in various fields, including image classification, speech recognition, and …

ArchExplorer: Microarchitecture exploration via bottleneck analysis

C Bai, J Huang, X Wei, Y Ma, S Li, H Zheng… - Proceedings of the 56th …, 2023 - dl.acm.org
Design space exploration (DSE) for microarchitecture parameters is an essential stage in
microprocessor design to explore the trade-offs among performance, power, and area …

Performance modeling and directives optimization for high-level synthesis on FPGA

J Zhao, L Feng, S Sinha, W Zhang… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
High-level synthesis (HLS) relies on the use of synthesis directives to generate digital
designs meeting a set of specifications. However, the selection of directives depends largely …

Adaptive threshold non-Pareto elimination: Re-thinking machine learning for system level design space exploration on FPGAs

P Meng, A Althoff, Q Gautier… - 2016 Design, Automation …, 2016 - ieeexplore.ieee.org
One major bottleneck of the system level OpenCL-to-FPGA design tools is their extremely
time consuming synthesis process (including place and route). The design space for a …

Graph neural networks for high-level synthesis design space exploration

L Ferretti, A Cini, G Zacharopoulos, C Alippi… - ACM Transactions on …, 2022 - dl.acm.org
High-level Synthesis (HLS) Design-Space Exploration (DSE) aims at identifying Pareto-
optimal synthesis configurations whose exhaustive search is unfeasible due to the design …