In this study, the negative DIBL (N-DIBL), negative differential resistance (NDR), and Miller
effect of a negative capacitance nanowire filed-effect-transistor (negative capacitance (NC) …

This article presents an analytical approach to estimate jitter in CMOS inverters in the
presence of ground-bounce noise (GBN). The relationships between output and input …

This article presents an analytical approach to determine jitter for a CMOS inverter in the
presence of power supply noise (PSN). The deviation in the transition edge of the output …

In this paper, an inverter logic gate has been successfully designed based on the previously
proposed side-contacted field-effect diodes (S-FEDs). Effect of the reservoir thickness on the …

With the advancement of semiconductor technology (enabling the dimensions of the
switching devices in the range of nanometer scale) designing, modeling, and optimization of …

Scaling down the supply voltage (V dd) below the transistors threshold voltage (V th) has
become a very popular technique in designing Ultra-Low-Power circuits whose demand has …

This study discusses and introduces the impact of variability on power supply-induced jitter
in integrated circuits. It presents an analytical approach to model timing uncertainty in the …

Low-power and high-speed logic gates and memory cells based on side-contacted field-
effect diodes (S-FED) exhibit considerably less overshoot and Miller-effect degradation …

Optical nanoscale computing is one promising alternative to the CMOS process. In this
paper we explore the application of Resonance Energy Transfer (RET) logic to common …

Due to the highly variation-prone nature of the near-threshold voltage (NTV) circuits, it is
critical to have design and performance models that consider process, voltage, and …