Classical molecular dynamics (MD) simulations have been performed for Cl+ and Br+ ions
incident on Si (100) surfaces with Cl and Br neutrals, respectively, to gain a better …

Plasma etching has long enabled the perpetuation of Moore's Law. Today, etch
compensation helps to create devices that are smaller than 20 nm. But, with the constant …

Classical molecular dynamics (MD) simulations have been performed for SiCl x+(x= 0–4)
ions incident on Si (100) surfaces, using an improved Stillinger–Weber (SW) potential form …

Atomic-or nanometer-scale surface roughening has been investigated during Si etching in
inductively coupled Cl 2 plasmas, as a function of rf bias power or ion incident energy E i, by …

Patterning complex metal gate stack becomes increasingly challenging since the gate
dimension for all isolated as well as dense gate structures present on 300 mm wafer needs …

Addition of oxygen to Cl 2 discharge is widely used in Si etching for the fabrication of gate
electrodes and shallow trench isolation. As the control of etching processes becomes more …

The authors have investigated the etch chamber recovery after TiN, TaN, and Hf O 2 metal
gate etching processes. The deposits formed on the reactor walls after etching these …

In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-
wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor …

In this study, we present a technique to analyze side wall passivation layers formed on
silicon sidewalls after plasma processing. The thickness and chemical composition are …

The integration of porous dielectric (low-k) in interconnects of integrated circuits is limited by
the damage induced by plasma processes to the porous material. Plasma-damaged …