6,071,775 A 6, 2000 Choi et al. 6,127,700 A 10, 2000 Bulucea. 6,166,954 A 12/2000 Chern
voltage; a second PMOS transistor comprising the second p-type doped region, a third p …

BACKGROUND Memory cells such as, for example, flash memory cells may be used to store
data. One type of flash memory cell is a split-gate flash memory cell, which may include a …

In an embodiment of the invention, a memory cell arrange ment includes a Substrate and at
least one memory cell includ ing a charge storing memory cell structure and a select struc …

(57) ABSTRACT A non-volatile memory (NVM) system has a normal mode, a standby mode
and an off mode that uses less power than the standby mode. The NVM system includes an …

BACKGROUND 0002 Among semiconductor devices, an electrically eras able
programmable read-only memory (EEPROM)-type flash memory device includes a floating …

In the non-volatile semiconductor memory device, a mobile charge collector layer, a mobile
charge collecting contact, a mobile charge collecting first wiring layer, an in-between contact …

FIG. 1 is a schematic cross-sectional view illustrating a conventional programmable dual-
poly nonvolatile memory. The programmable dual-poly nonvolatile memory is also referred …

A transistor arrangement includes a switch transistor and a sense transistor. The switch
transistor includes a charge storing structure and a control structure. The sense transistor …

A number of circuits for use in an output block coupled to a non-volatile memory array in a
neural network are disclosed. The embodiments include a circuit for converting an output …

A device having at least one memory cell over a substrate is provided. The at least one
memory cell includes a source region and a drain region in the substrate, and a first gate …