This paper presents a self adaptive architecture to enhance the energy efficiency of coarse-
grained reconfigurable architectures (CGRAs). Today, platforms host multiple applications …

We present an adaptive energy management system for dynamically reconfigurable
processors that chooses an energy-minimizing set of custom instructions (CIs) and then …

Hardware/software (HW/SW) partitioning and task scheduling are the crucial steps of
HW/SW co-design. It is very difficult to achieve the optimal solution as both scheduling and …

The hardware/software (HW/SW) partitioning is a major concern in heterogeneous multi-
processor system-on-a-chip design, where the large design space prohibits rapid …

Reconfigurable processors provide a means to flexible and energy-aware computing. In this
paper, we present a new scheme for runtime energy minimization (REMiS) as part of a …

Warp processing is a recent computing technology capable of autonomously partitioning the
critical kernels within an executing software application to hardware circuits implemented …

Significant research has demonstrated the performance and power benefits of runtime
dynamic reconfiguration of FPGAs and microprocessor/FPGA devices. For dynamically …

In the era of platforms hosting multiple applications with arbitrary performance requirements,
providing a worst-case platform-wide voltage/frequency operating point is neither optimal …

We propose a new way to save energy in adaptive processors. According to an execution
context the custom instruction set of an adaptive processor is selectively'muted'at run time …

Reusing off-the-shelf components is burgeoning in systems-on-chip design. Compatibility
problems however are common as these components are typically heterogeneous and …