A self-trimming 14-b 100-MS/s CMOS DAC

AR Bugeja, BS Song - IEEE Journal of Solid-State Circuits, 2000 - ieeexplore.ieee.org
A 14-b 100-MS/s CMOS digital-analog converter (DAC) designed for high static and
dynamic linearity is presented. The DAC is based on a central core of 15 thermometer …

[图书][B] Advanced data converters

G Manganaro - 2011 - books.google.com
Need to get up to speed quickly on the latest advances in high performance data
converters? Want help choosing the best architecture for your application? With everything …

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

J Hyde, T Humes, C Diorio, M Thomas… - IEEE Journal of Solid …, 2003 - ieeexplore.ieee.org
Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog
converter (DAC) fabricated in 0.25-and 0.18-μm CMOS logic processes. We trim the static …

[图书][B] Dynamic characterisation of analogue-to-digital converters

D Dallet, JM da Silva - 2006 - books.google.com
The Analogue-to-digital converter (ADC) is the most pervasive block in electronic systems.
With the advent of powerful digital signal processing and digital communication techniques …

A 13-bit, 2.2-MS/s, 55-mW multibit cascade/spl Sigma//spl Delta/modulator in CMOS 0.7-/spl mu/m single-poly technology

F Medeiro, B Perez-Verdu… - IEEE Journal of Solid …, 1999 - ieeexplore.ieee.org
This paper presents a CMOS 0.7-/spl mu/m/spl Sigma//spl Delta/modulator IC that achieves
13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential …

[图书][B] Direct conversion receivers in wide-band systems

A Pärssinen - 2001 - Springer
The development of the mobile communications systems has come to the era when most of
the signal processing is performed digitally. The advantages of digital communications for …

An improved switch compensation technique for inverted R-2R ladder DACs

D Marche, Y Savaria, Y Gagnon - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Many recent applications are based on DSPs interfaced to analog I/0s with data converters.
In this context, high-performance DACs have become crucial building blocks. The current …

A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25/spl mu/m CMOS

J Hyde, T Humes, C Diorio, M Thomas… - 2002 Symposium on …, 2002 - ieeexplore.ieee.org
We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a
0.25/spl mu/m CMOS logic process. We trim the static INL to/spl plusmn/0.3 LSB using …

Floating-point analog-to-digital converter

J Yuan, J Piper - ICECS'99. Proceedings of ICECS'99. 6th IEEE …, 1999 - ieeexplore.ieee.org
A floating-point ADC (FP-ADC) has been proposed for the purpose of achieving a wide
dynamic range without demanding a high resolution, when the high resolution is merely for …

[图书][B] Radio resource management in wireless communication: Beamforming, transmission power control, and rate allocation

V Hasu - 2007 - aaltodoc.aalto.fi
Effective sharing of the radio spectrum in current and future multi-user radio communication
systems is important for the maximisation of communication capacity. Efficient sharing …