[HTML][HTML] Progress in the development and understanding of advanced low k and ultralow k dielectrics for very large-scale integrated interconnects—State of the art

A Grill, SM Gates, TE Ryan, SV Nguyen… - Applied Physics …, 2014 - pubs.aip.org
The improved performance of the semiconductor microprocessors was achieved for several
decades by continuous scaling of the device dimensions while using the same materials for …

PECVD low and ultralow dielectric constant materials: From invention and research to products

A Grill - Journal of Vacuum Science & Technology B, 2016 - pubs.aip.org
This paper is based on the 2015 AVS John A. Thornton Memorial Award Lecture. In 2015,
the semiconductor industry celebrated the 50th anniversary of Moore's law, which has been …

FPGA-based prototype of a PRAM-on-chip processor

X Wen, U Vishkin - Proceedings of the 5th conference on Computing …, 2008 - dl.acm.org
PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel
machine model for many years, but it is also believed to be" impossible in reality." As the …

Advanced single precursor based pSiCOH k= 2.4 for ULSI interconnects

D Priyadarshini, SV Nguyen, H Shobha… - Journal of Vacuum …, 2017 - pubs.aip.org
A single precursor, octamethylcyclotetrasiloxane (OMCTS), was used to develop a pSiCOH
interconnect dielectric with an ultralow dielectric constant k ¼2. 4. With no added porogen …

Interconnect Processing: Integration, Dielectrics, Metals

ST Chen, NA Lanzillo, S Van Nguyen, T Nogami… - Springer Handbook of …, 2022 - Springer
This chapter covers integration, performance, and three main process sectors concerning
back-end-of-line (BEOL) wiring (“interconnect”) process technology: intralevel dielectrics …

Low and ultralow dielectric constant films prepared by plasma‐enhanced chemical vapor deposition

A Grill - Dielectric films for advanced microelectronics, 2007 - Wiley Online Library
The semiconductor industry has been improving the performance of ultra-large-scale
integrated (ULSI) circuits by shrinking the transistor size according to Moore's Law, which …

Distinctive features and problems of CMOS technology for decrease in the node size to 0.18 μm or less

GY Krasnikov, OM Orlov - Nanotechnologies in Russia, 2008 - Springer
The main problems and distinctive features in developing CMOS VLSI technology are
considered for a decrease in the node size to 0.18 μm or less. This becomes possible on the …

[图书][B] Hardware design, prototyping and studies of the explicit multi-threading (XMT) paradigm

X Wen - 2008 - search.proquest.com
With the end of exponential performance improvements in sequential computers, parallel
computers, dubbed" chip multiprocessor"," multicore", or" manycore", has been introduced …

Spin-on dielectric materials

G Dubois, RD Miller, W Volksen - Dielectric films for advanced …, 2007 - Wiley Online Library
As device sizes decrease and device densities increase, chip performance will begin to
erode without modified materials. This is a significant problem for the semiconductor industry …

Residual-photoresist removal from Si and GaAs surfaces by atomic-hydrogen flow treatment

EV Anishchenko, VA Kagadei, EV Nefedtsev… - Russian …, 2005 - Springer
It is shown by experiment that a directed atomic-hydrogen stream offers a means of residual-
photoresist removal from Si and GaAs surfaces. The dependence of postprocess surface …