Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms
The energy consumption of DRAM is a critical concern in modern computing systems.
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
Improvements in manufacturing process technology have allowed DRAM vendors to lower …
The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
Understanding rowhammer under reduced wordline voltage: An experimental study using real dram devices
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
Are we susceptible to rowhammer? an end-to-end methodology for cloud providers
Cloud providers are concerned that Rowhammer poses a potentially critical threat to their
servers, yet today they lack a systematic way to test whether the DRAM used in their servers …
servers, yet today they lack a systematic way to test whether the DRAM used in their servers …
QUAC-TRNG: High-throughput true random number generation using quadruple row activation in commodity DRAM chips
True random number generators (TRNG) sample random physical processes to create large
amounts of random numbers for various use cases, including security-critical cryptographic …
amounts of random numbers for various use cases, including security-critical cryptographic …
Improving 3D NAND flash memory lifetime by tolerating early retention loss and process variation
Compared to planar (ie, two-dimensional) NAND flash memory, 3D NAND flash memory
uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip …
uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip …
Benchmarking memory-centric computing systems: Analysis of real processing-in-memory hardware
Many modern workloads such as neural network inference and graph processing are
fundamentally memory-bound. For such workloads, data movement between memory and …
fundamentally memory-bound. For such workloads, data movement between memory and …
In-memory low-cost bit-serial addition using commodity DRAM technology
In-memory computing architectures present a promising solution to address the memoryand
the power-wall challenges by mitigating the bottleneck between processing units and …
the power-wall challenges by mitigating the bottleneck between processing units and …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …