Understanding and improving the latency of DRAM-based memory systems
KK Chang - 2017 - search.proquest.com
Over the past two decades, the storage capacity and access bandwidth of main memory
have improved tremendously, by 128x and 20x, respectively. These improvements are …
have improved tremendously, by 128x and 20x, respectively. These improvements are …
Understanding and modeling on-die error correction in modern DRAM: An experimental study using real devices
Experimental characterization of DRAM errors is a powerful technique for understanding
DRAM behavior and provides valuable insights for improving overall system performance …
DRAM behavior and provides valuable insights for improving overall system performance …
DR-STRaNGe: end-to-end system design for DRAM-based true random number generators
Random number generation is an important task in a wide variety of critical applications
including cryptographic algorithms, scientific simulations, and industrial testing tools. True …
including cryptographic algorithms, scientific simulations, and industrial testing tools. True …
HARP: Practically and effectively identifying uncorrectable errors in memory chips that use on-die error-correcting codes
Aggressive storage density scaling in modern main memories causes increasing error rates
that are addressed using error-mitigation techniques. State-of-the-art techniques for …
that are addressed using error-mitigation techniques. State-of-the-art techniques for …
Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions
Read disturbance in modern DRAM chips is a widespread phenomenon and is reliably used
for breaking memory isolation, a fundamental building block for building robust systems …
for breaking memory isolation, a fundamental building block for building robust systems …
A case for self-managing DRAM chips: Improving performance, efficiency, reliability, and security via autonomous in-DRAM maintenance operations
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
Reducing DRAM latency via charge-level-aware look-ahead partial restoration
Long DRAM access latency is a major bottleneck for system performance. In order to access
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …
A case for transparent reliability in DRAM systems
Today's systems have diverse needs that are difficult to address using one-size-fits-all
commodity DRAM. Unfortunately, although system designers can theoretically adapt …
commodity DRAM. Unfortunately, although system designers can theoretically adapt …
Whistleblower: A system-level empirical study on rowhammer
With frequent software-induced activations on DRAM rows, bit flips can occur on their
physically adjacent rows (ie, RowHammer). Existing studies leverage FPGA platforms to …
physically adjacent rows (ie, RowHammer). Existing studies leverage FPGA platforms to …
Errors in flash-memory-based solid-state drives: Analysis, mitigation, and recovery
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …
continuously increased and cost has continuously decreased over decades. This positive …