Dramscope: Uncovering dram microarchitecture and characteristics by issuing memory commands
The demand for precise information on DRAM microarchitectures and error characteristics
has surged, driven by the need to explore processing in memory, enhance reliability, and …
has surged, driven by the need to explore processing in memory, enhance reliability, and …
Amplifying Main Memory-Based Timing Covert and Side Channels using Processing-in-Memory Operations
The adoption of processing-in-memory (PiM) architectures has been gaining momentum
because they provide high performance and low energy consumption by alleviating the data …
because they provide high performance and low energy consumption by alleviating the data …
Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes
M Patel - arXiv preprint arXiv:2204.10387, 2022 - arxiv.org
Improvements in main memory storage density are primarily driven by process technology
scaling, which negatively impacts reliability by exacerbating various circuit-level error …
scaling, which negatively impacts reliability by exacerbating various circuit-level error …
Extending Memory Capacity in Modern Consumer Systems With Emerging Non-Volatile Memory: Experimental Analysis and Characterization Using the Intel Optane …
DRAM scalability is becoming a limiting factor to the available memory capacity in consumer
devices. As a potential solution, manufacturers have introduced emerging non-volatile …
devices. As a potential solution, manufacturers have introduced emerging non-volatile …
WoLFRaM: Enhancing wear-leveling and fault tolerance in resistive memories using programmable address decoders
Resistive memories have limited lifetime caused by limited write endurance and highly non-
uniform write access patterns. Two main techniques to mitigate endurance-related memory …
uniform write access patterns. Two main techniques to mitigate endurance-related memory …
Sectored DRAM: An energy-efficient high-throughput and practical fine-grained DRAM architecture
There are two major sources of inefficiency in computing systems that use modern DRAM
devices as main memory. First, due to coarse-grained data transfers (size of a cache block …
devices as main memory. First, due to coarse-grained data transfers (size of a cache block …
DRAM retention behavior with accelerated aging in commercial chips
The cells in dynamic random access memory (DRAM) degrade over time as a result of
aging, leading to poor performance and potential security vulnerabilities. With a globalized …
aging, leading to poor performance and potential security vulnerabilities. With a globalized …
Refresh triggered computation: Improving the energy efficiency of convolutional neural network accelerators
To employ a Convolutional Neural Network (CNN) in an energy-constrained embedded
system, it is critical for the CNN implementation to be highly energy efficient. Many recent …
system, it is critical for the CNN implementation to be highly energy efficient. Many recent …
Architectural techniques for improving NAND flash memory reliability
Y Luo - arXiv preprint arXiv:1808.04016, 2018 - arxiv.org
Raw bit errors are common in NAND flash memory and will increase in the future. These
errors reduce flash reliability and limit the lifetime of a flash memory device. We aim to …
errors reduce flash reliability and limit the lifetime of a flash memory device. We aim to …
Understanding Read Disturbance in High Bandwidth Memory: An Experimental Analysis of Real HBM2 DRAM Chips
DRAM read disturbance is a significant and worsening safety, security, and reliability issue
of modern DRAM chips that can be exploited to break memory isolation. Two prominent …
of modern DRAM chips that can be exploited to break memory isolation. Two prominent …