Timing Side-Channel Attacks and Countermeasures in CPU Microarchitectures

J Zhang, C Chen, J Cui, K Li - ACM Computing Surveys, 2024 - dl.acm.org
Microarchitectural vulnerabilities, such as Meltdown and Spectre, exploit subtle
microarchitecture state to steal the user's secret data and even compromise the operating …

Leaky frontends: Security vulnerabilities in processor frontends

S Deng, B Huang, J Szefer - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
This paper evaluates new security threats due to the processor frontend in modern Intel
processors. The root causes of the security threats are the multiple paths in the processor …

WRITE+ SYNC: Software Cache Write Covert Channels Exploiting Memory-disk Synchronization

C Chen, J Cui, G Qu, J Zhang - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Memory-disk synchronization is a critical technology for ensuring data correctness, integrity,
and security, especially in systems that handle sensitive information like financial …

Sok: Analysis of root causes and defense strategies for attacks on microarchitectural optimizations

NR Holtryd, M Manivannan… - 2023 IEEE 8th European …, 2023 - ieeexplore.ieee.org
Microarchitectural optimizations are expected to play a crucial role in ensuring performance
scalability in the post-Moore era. However, recent attacks have demonstrated that these …

Improving Multicore Architectures by Selective Value Prediction of High-Latency Arithmetic Instructions.

C BUDULECI, A GELLERT… - … in Electrical & …, 2024 - search.ebscohost.com
This work is an original contribution consisting in the implementation and evaluation of a
selective value predictor in a multicore environment, with focus on long latency arithmetical …

SYNC+ SYNC: Software Cache Write Covert Channels Exploiting Memory-disk Synchronization

C Chen, J Cui, G Qu, J Zhang - arXiv preprint arXiv:2312.11501, 2023 - arxiv.org
Memory-disk synchronization is a critical technology for ensuring data correctness, integrity,
and security, especially in systems that handle sensitive information like financial …

SPECRUN: The Danger of Speculative Runahead Execution in Processors

C Shen, G Qu, J Zhang - arXiv preprint arXiv:2312.01832, 2023 - arxiv.org
Runahead execution is a continuously evolving microarchitectural technique for processor
performance. This paper introduces the first transient execution attack on the runahead …

Processor Microarchitecture Security

S Deng - 2022 - search.proquest.com
As computer systems grow more and more complicated, various optimizations can
unintentionally introduce security vulnerabilities in these systems. The vulnerabilities can …