Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …

As memory scales down to smaller technology nodes, new failure mechanisms emerge that
threaten its correct operation. If such failure mechanisms are not anticipated and corrected …

Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …

Cloud providers are concerned that Rowhammer poses a potentially critical threat to their
servers, yet today they lack a systematic way to test whether the DRAM used in their servers …

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …

True random number generators (TRNG) sample random physical processes to create large
amounts of random numbers for various use cases, including security-critical cryptographic …

Multirate refresh techniques exploit the non-uniformity in retention times of DRAM cells to
reduce the DRAM refresh overheads. Such techniques rely on accurate profiling of retention …

We provide an overview of recent developments and future directions in the RowHammer
vulnerability that plagues modern DRAM (Dynamic Random Memory Access) chips, which …

Many modern workloads such as neural network inference and graph processing are
fundamentally memory-bound. For such workloads, data movement between memory and …

The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …