An introduction to the compute express link (cxl) interconnect
DD Sharma, R Blankenship, DS Berger - arXiv preprint arXiv:2306.11227, 2023 - arxiv.org
The Compute Express Link (CXL) is an open industry-standard interconnect between
processors and devices such as accelerators, memory buffers, smart network interfaces …
processors and devices such as accelerators, memory buffers, smart network interfaces …
PARBOR: An efficient system-level technique to detect data-dependent failures in DRAM
System-level detection and mitigation of DRAM failures offer a variety of system
enhancements, such as better reliability, scalability, energy, and performance. Unfortunately …
enhancements, such as better reliability, scalability, energy, and performance. Unfortunately …
DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …
Demystifying complex workload-DRAM interactions: An experimental study
It has become increasingly difficult to understand the complex interactions between modern
applications and main memory, composed of Dynamic Random Access Memory (DRAM) …
applications and main memory, composed of Dynamic Random Access Memory (DRAM) …
In-DRAM bulk bitwise execution engine
V Seshadri, O Mutlu - arXiv preprint arXiv:1905.09822, 2019 - arxiv.org
Many applications heavily use bitwise operations on large bitvectors as part of their
computation. In existing systems, performing such bulk bitwise operations requires the …
computation. In existing systems, performing such bulk bitwise operations requires the …
Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
Detecting and mitigating data-dependent DRAM failures by exploiting current memory content
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …
These failures are called data-dependent failures. Detecting and mitigating these failures …
Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability
DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …
trends in multi-core system design and large-dataset applications have amplified the role of …
An experimental analysis of RowHammer in HBM2 DRAM chips
RowHammer (RH) is a significant and worsening security, safety, and reliability issue of
modern DRAM chips that can be exploited to break memory isolation. Therefore, it is …
modern DRAM chips that can be exploited to break memory isolation. Therefore, it is …
DASH: Deadline-aware high-performance memory scheduler for heterogeneous systems with hardware accelerators
H Usui, L Subramanian, KKW Chang… - ACM Transactions on …, 2016 - dl.acm.org
Modern SoCs integrate multiple CPU cores and hardware accelerators (HWAs) that share
the same main memory system, causing interference among memory requests from different …
the same main memory system, causing interference among memory requests from different …