Reducing DRAM latency at low cost by exploiting heterogeneity

D Lee - arXiv preprint arXiv:1604.08041, 2016 - arxiv.org
In modern systems, DRAM-based main memory is significantly slower than the processor.
Consequently, processors spend a long time waiting to access data from main memory …

Accelerating Personalized Recommendation with Cross-level Near-Memory Processing

H Liu, L Zheng, Y Huang, C Liu, X Ye, J Yuan… - Proceedings of the 50th …, 2023 - dl.acm.org
The memory-intensive embedding layers of the personalized recommendation systems are
the performance bottleneck as they demand large memory bandwidth and exhibit irregular …

Reliability issues in flash-memory-based solid-state drives: Experimental analysis, mitigation, recovery

Y Cai, S Ghose, EF Haratsch, Y Luo, O Mutlu - Inside Solid State Drives …, 2018 - Springer
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …

Quantifying memory underutilization in hpc systems and using it to improve performance via architecture support

G Panwar, D Zhang, Y Pang, M Dahshan… - Proceedings of the …, 2019 - dl.acm.org
A system's memory size is often dictated by worst-case workloads with highest memory
requirements; this causes memory to be underutilized in the common case when the system …

The main memory system: Challenges and opportunities

O Mutlu, J Meza, L Subramanian - Communications of the Korean …, 2015 - koreascience.kr
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

Main memory scaling: Challenges and solution directions

O Mutlu - More than Moore technologies for next generation …, 2015 - Springer
The memory system is a fundamental performance and energy bottleneck in almost all
computing systems. Recent system design, application, and technology trends that require …

The processing-in-memory paradigm: Mechanisms to enable adoption

S Ghose, K Hsieh, A Boroumand… - … -CMOS Technologies for …, 2019 - Springer
Performance improvements from DRAM technology scaling have been lagging behind the
improvements from logic technology scaling for many years. As application demand for main …

Omitting refresh: A case study for commodity and wide i/o drams

M Jung, É Zulian, DM Mathew, M Herrmann… - Proceedings of the …, 2015 - dl.acm.org
Dynamic Random Access Memories (DRAM) have a big impact on performance and
contribute significantly to the total power consumption in systems ranging from mobile …

[PDF][PDF] Architectural techniques to enhance DRAM scaling

Y Kim - Ph. D. dissertation, Carnegie Mellon University, 2015 - kilthub.cmu.edu
For decades, main memory has enjoyed the continuous scaling of its physical substrate:
DRAM (DynamicRandomAccessMemory). Butnow, DRAMscalinghasreachedathreshold …

Dream: Dynamic re-arrangement of address mapping to improve the performance of drams

M Ghasempour, A Jaleel, JD Garside… - Proceedings of the …, 2016 - dl.acm.org
The initial location of data in DRAMs is determined and controlled by the'address-
mapping'and even modern memory controllers use a fixed and run-time-agnostic address …