Hardware virtualization has been increasingly used to provide performance isolation
between multiple tenants sharing an SSD. It exploits the SSD's highly parallel architecture …

Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive
increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error …

Address mapping for flash storage devices has been a challenging design issue for
controllers because of rapidly growing device capacity. In contrast with existing mapping …

In recent years, multi-level cell flash memory (MLC) has been widely adopted in solid state
drives (SSD's) as the major storage medium due to its lower cost and higher density …

LDPC code is introduced in NAND flash memory to handle high BER (bit error rate) incurred
by technology scaling. Despite strong error correction capability, LDPC decoding induces …

Program disturb, read disturb, and retention time noise are identified as three major
contributors to multilevel cell (MLC) NAND flash memory bit errors. With program/erase …

A major limitation of NAND flash memory is erase-before-program characteristics. It incurs
write amplification, severely degrading system performance and endurance. Previous works …

Triple-level-ceil (MLCx3) flash-memory chips are prevalent in current storage markets;
however, the growing bit-error-rate and worsen reliability of TLC flash ceils impose …

Deep Neural Networks (DNNs) offer remarkable performance of classifications and
regressions in many high dimensional problems and have been widely utilized in real-word …

Spaceborne detection can obtain more direct, comprehensive and accurate astronomical
data. Providing massive storage for spaceborne applications is the urgent requirement of …