A prototyping system for verification and evaluation in hardware-software cosynthesis
T Benner, R Ernst, I Konenkamp… - … Workshop on Rapid …, 1995 - ieeexplore.ieee.org
We present a system emulator for rapid prototyping of small embedded HW/SW-systems
with hard timing constraints generated by a HW/SW cosynthesis system. It consists of a …
with hard timing constraints generated by a HW/SW cosynthesis system. It consists of a …
Hybrid cache analysis in running time verification of embedded software
F Wolf, J Staschulat, R Ernst - Design Automation for Embedded Systems, 2002 - Springer
Verification of software running time is essential in embedded systemdesign with real-time
constraints. Simulation with incomplete test patternsis unsafe for complex architectures …
constraints. Simulation with incomplete test patternsis unsafe for complex architectures …
FPGA based prototyping for verification and evaluation in hardware-software cosynthesis
T Benner, R Ernst, I Könenkamp, U Holtmann… - … and Applications: 4th …, 1994 - Springer
Abstract COSYMA is a HW/SW-cosynthesis system for small embedded controllers. The final
simulation of the COSYMA output leads to impractical computation time. Therefore, we …
simulation of the COSYMA output leads to impractical computation time. Therefore, we …
Speed-up estimation for HW/SW-systems
W Hardt, W Rosenstiel - Proceedings of 4th International …, 1996 - ieeexplore.ieee.org
HW/SW-codesign has been applied to a wide range of applications. Several partitioning
methods have been suggested. Thus the designer selects modules for HW or SW …
methods have been suggested. Thus the designer selects modules for HW or SW …
VCore-based design methodology
M Muraoka, H Hamada, H Nishi, T Tada… - Proceedings of the …, 2003 - dl.acm.org
The VCore [1](*) based design methodology, which has been developed at the VCDS (**)
Project, is a SoC design methodology using VCores. A VCore is a reusable, high level …
Project, is a SoC design methodology using VCores. A VCore is a reusable, high level …
A hardware-software codesign strategy for loop intensive applications
Y Zhang, M Kandemir - 2009 IEEE 7th Symposium on …, 2009 - ieeexplore.ieee.org
Hardware-software codesign is a powerful technique that can be used to build complex
systems. In this paper, we propose a compiler driven hardware-software codesign strategy …
systems. In this paper, we propose a compiler driven hardware-software codesign strategy …
[PDF][PDF] A Performance Evaluator for Parameterized ASIC Architectures y
Abstract System-level partitioning assigns functional objects such as tasks or code segments
to system-level components such as o-the-shelf processors or application-specific …
to system-level components such as o-the-shelf processors or application-specific …
On the use of distributed reconfigurable hardware in launch control avionics
BE Wells, SM Loo - 20th DASC. 20th Digital Avionics Systems …, 2001 - ieeexplore.ieee.org
This paper discusses the feasibility of employing reconfigurable hardware in the avionics
systems of future generations of launch vehicles for space. Such technology has the …
systems of future generations of launch vehicles for space. Such technology has the …
Profiling in the ASP codesign environment
MF Parkinson, S Parameswaran - … of the 8th international symposium on …, 1995 - dl.acm.org
Automation of the hardware/software codesign methodology brings with it the need to
develop sophisticated high-level profiling tools. This paper presents a profiling tool which …
develop sophisticated high-level profiling tools. This paper presents a profiling tool which …