In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and
junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In …

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the
gate, with SiC layers under the source and drain, to improve the leakage current and thermal …

A novel and practicable partial punch-through-stopper (p-PTS) scheme beneath the gate
area is proposed for the substrate leakage current suppression in the gate-all-around (GAA) …

This work investigates the characteristics and reliability of double-gate (DG) and single-gate
(SG) mode operations in polycrystalline-silicon nanosheet transistors (TFTs). It is observed …

As complementary metal-oxide semiconductor (CMOS) is scaled down to achieve higher
chip density, thin-film layers have been deposited iteratively. The poor film uniformity …