In an embodiment, a processor may implement an access map-pattern match (AMPM)-
based prefetch circuit for a multi-level cache system. The access patterns that are matched …

Described apparatuses and methods track access metadata pertaining to activity within
respective address ranges. The access metadata can be used to inform prefetch operations …

Described is a computing system for vector prefetching which includes a hierarchical
memory including multiple caches, a missing address storage unit (MASU) associated with …

In one embodiment, a bounding box prefetch unit in a microprocessor, the bounding box
prefetch unit comprising: storage comprising a plurality of active prefetcher state entries for …

Described apparatuses and methods form adaptive cache lines having a configurable
capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can …

Described is a computing system and method for differential cache block sizing for
computing systems. The method for differential cache block sizing includes determining …

Described apparatuses and methods track access metadata pertaining to activity within
respective address ranges. The access metadata can be used to inform prefetch operations …

In an embodiment, a processor includes a plurality of prefetch circuits configured to prefetch
data into a data cache. A primary prefetch circuit may be configured to generate first prefetch …

A system and method including a processor configured to, based on encountering an
instruction that does not modify the architectural state of the processor, preferably a prefetch …

A variety of data processing apparatuses are provided in which stride determination circuitry
determines a stride value as a difference between a current address and a previously …