(57) ABSTRACT A System and method for configuration of a programmable logic device
using routing cores. A program executing on a processor includes instructions that Select …

A circuit arrangement includes a programmable logic device. The programmable logic
device includes configuration logic circuitry. The programmable logic device also includes …

A time synchronized measurement system has a master device and a slave device. The
master device and the slave device each have a time measurement device for assigning a …

US20080221834A1 - Method and system for enhanced fault detection workflow - Google Patents
US20080221834A1 - Method and system for enhanced fault detection workflow - Google Patents …

A system and method for evolving configuration bitstreams for a programmable logic device
are disclosed. A plurality of data structures having respective sets of data are established …

In one embodiment, a programmable logic device includes a plurality of logic blocks; a
plurality of input/output blocks; volatile configuration memory adapted to store configuration …

One FPGA provides a multiplexer that allows a host CPU to directly access a second FPGA's
memory for upgrading. The second FPGA acts as a buffer and does not participate directly in …

5,598.409 5,606,672 5,615,344 5,621,902 5,628,001 5,630,147 5,634,074 5,642.489
5,655,148 5,671,355 5,673,031 5,675,813 5,687,346 5,701.429 5,748,911 5,748,923 …

The present invention relates generally to the field of configuring a programmable logic
device (PLD) Such as a Field Programmable Gate Array (FPGA), and more specifi cally to …

(57) ABSTRACT A method and apparatus for developing run-time parameter izable logic
cores for programmable logic devices (PLDS). In various embodiments, logic cores are …