(57) ABSTRACT A reconfigurable data processor comprises an array of configurable units
and a bus system configurable to define virtual machines. The system can partition the array …

Methods and systems for firewall/data protection that filters data packets in real time and
without packet buffering are disclosed. A data packet filtering hub, which may be imple …

BACKGROUND 0003. Many similarities exist between seemingly unre lated designs in
consumer, industrial, and telecommunication electronics. Examples of similarities include …

BACKGROUND Programmable logic devices (PLDs), such as field pro grammable gate
arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with …

US PATENT DOCUMENTS 4,641.261 A 2/1987 Dwyer et al. 4,701,913 A 10, 1987 Nelson
4,713,757 A 12/1987 Davidson et al. 4,862,355 A 8, 1989 Newman et al. 4.866, 606 A …

A system and method for evolving configuration bitstreams for a programmable logic device
are disclosed. A plurality of data structures having respective sets of data are established …

5,640,106 A 6, 1997 Erickson et al. 5,794,033 A* 8/1998 Aldebert et al.............. T13/100
6,326,806 B1* 12/2001 Fallside et al................. 326/38 6,614,259 B2* 9/2003 Couts-Martin et …

BACKGROUND Clock signals for electrical devices may be constrained by a number of error
sources. For example, these error sources may include delay variations among signals for a …

In one embodiment, a data decompression circuit for a data stream having a repeated data
word is provided. The data stream is compressed into a series of data frames such that the …

5,428,748 5,461,723 5.488, 657 5,574,859 5,577,213 5,586,268 5,606,672 5,615,344
5,621,902 5,628,001 5,630,147 5,634,074 5,642.489 5,671,355 5,675,813 5,687,346 …