As von Neumann computing architectures become increasingly constrained by data-
movement overheads, researchers have started exploring in-memory computing (IMC) …

In this paper, quadruple cross-coupled storage cells (QUCCE) 10T and 12T are proposed in
130 nm CMOS technology. The QUCCE 10T and 12T are about 2× and 3.4× the minimum …

This work introduces the±CIM SRAM macro having the unique capability of performing in-
memory multiply-and-accumulate computation with signed inputs and signed weights. This …

This paper presents a process voltage temperature (PVT)‐variation‐tolerant Schmitt‐trigger‐
based 12T SRAM cell at 32 nm. The cell uses a modified Schmitt‐trigger action in all …

A compute SRAM requires high speed for both compute access and normal read access.
However, it presents a very distinct bitline discharging behavior in these two modes, thus …

In this article, we present an energy-efficient high bandwidth array design using 0.0300-high-
performance SRAM bitcell on Intel 4 CMOS technology. By employing a unique combination …

In this article, we present a 4.13-GHz ultrahigh-speed (UHS) pseudo two-port SRAM for high-
performance computing (HPC) in 4-nm FinFET technology. By applying the bitline (BL) …

An effective design is proposed to reduce dynamic power consumption for a common clock
synchronous two-read/write (2RW) dual-port (DP) 8T static random access memory (SRAM) …

The growing processing load and decreasing technology node has augmented the need for
single ended memory. Consequently, generating requirement for a single ended sense …

This paper presents a new methodology for automating the Computational SRAM (C-SRAM)
design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal …