High-performance 32-bit parallel hybrid adder design using RNS and hybrid PTL/CMOS logic
A Khairnar, B Chauhan, G Sharma… - Journal of Circuits …, 2022 - World Scientific
Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the
memory, table indices and many more such types of applications. The speed of the adder …
memory, table indices and many more such types of applications. The speed of the adder …
Performance investigation of electrical parameters of OTFT for different dielectric materials
Gate dielectrics have a significant impact on transistor performance. The selection of
dielectric material is critical in the design of organic thin film transistor (OTFT). This study …
dielectric material is critical in the design of organic thin film transistor (OTFT). This study …
[PDF][PDF] Design of two stage differential amplifier with stacked transistors for biomedical applications
P Jain, SDS Sharma, AM Joshi… - Wirel Personal …, 2021 - pdfs.semanticscholar.org
In this paper, CMOS based optimized two stage differential amplifier circuit for convenient
biomedical signal conditioning system is presented. A low-power, low noise & high CMRR …
biomedical signal conditioning system is presented. A low-power, low noise & high CMRR …
Design of single poly flash memory cell with power reduction technique at program mode in 65nm CMOS process
CJ Sagario, B Quidlat, KG Jimenez… - 2018 International …, 2018 - ieeexplore.ieee.org
This paper focuses on the bit lines in the design of a single-poly flash memory cell during
program operation. A conventional flash memory cell uses a floating gate transistor where …
program operation. A conventional flash memory cell uses a floating gate transistor where …
Optimization of area and power in multi-mode power gating scheme for static memory elements
X Su, S Kimura - 2016 IEEE Asia Pacific Conference on …, 2016 - ieeexplore.ieee.org
This paper presents an optimization method of area and power for static memory elements
by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces …
by using multi-mode power gating (MMPG) scheme. A 2-transistor MMPG scheme replaces …
Analysis of static noise margin for novel power gated sram
BS Kumar, AM Joshi - ICTACT …, 2016 - repository.journal4submission.com
Data stability is one of the important parameter of SRAM with scaling of CMOS technology.
However the move to nanometer technology not only nodes has increased, but the …
However the move to nanometer technology not only nodes has increased, but the …
Power Efficient Dynamic Comparator for High Speed Digital Circuit
ADCs (Analog-Digital converters) are the main designing elements & implemented in
various applications for digitization of the signals. The dynamic comparator is one of the …
various applications for digitization of the signals. The dynamic comparator is one of the …
[图书][B] Next Generation Dynamically Reconfigurable DSP in 16nm Technology
UY Rathore - 2018 - search.proquest.com
An increasing number of dedicated accelerators in modern System on Chips (SoCs) have
led to large regions of dark silicon. Although highly efficient, these accelerators (ASICs) are …
led to large regions of dark silicon. Although highly efficient, these accelerators (ASICs) are …
Low Power Single Bit-line Power-gated SRAM
AP Inamdar, HVR Aradhya - 2018 3rd IEEE International …, 2018 - ieeexplore.ieee.org
A system-on-chip contains various components of which memory is one of the prominent
block. As the technology is growing and portable devices are taking charge of all our digital …
block. As the technology is growing and portable devices are taking charge of all our digital …
[引用][C] Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture
Static random access memory (SRAM) is a sort of RAM where information is not
permanently stored and does not require routine updating. To reduce leakage power without …
permanently stored and does not require routine updating. To reduce leakage power without …