A programmable memory cell comprised of a transistor located at the crosspoint of a column
bitline and a row wordline is disclosed. The transistor has its gate formed from the column …

A number of designs for differential floating gate nonvolatile memories and memory arrays
utilize differential pFET floating gate transistors to store information. Methods of …

4,507,757 A 3/1985 McElroy..................... 365/104 A programmable memory cell comprised
of a transistor 4,543,594 A 9/1985 Mohsen et al.............. 257/530 located at the croSSpoint of …

(63) Continuation-in-part of application No. 10/677,613, filed on () Oct. 2, 2003, which is a
continuation-in-part of application Primary Examiner-Gene N. Auduong No. 10/448,505, filed …

A reprogrammable non-volatile memory array and constituent memory cells is disclosed.
The semiconductor memory cells each have a data storage element constructed around an …

A semiconductor memory cell having a data storage element constructed around an ultra-
thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin …

An erasable programmable read only memory comprising two serially connected P-type
metal-oxide semiconductor (MOS) transistors wherein the control gate is omitted in the …

US6972986B2 - Combination field programmable gate array allowing dynamic
reprogrammability and non-votatile programmability based upon transistor gate oxide …

An erasable programmable single-poly nonvolatile memory includes a floating gate
transistor having a floating gate, a gate oxide layer under the floating gate, and a channel …

A semiconductor memory cell having a data storage element constructed around an ultra-
thin dielectric, such as a gate oxide, is used to store information by stressing the ultra-thin …