High speed, high voltage tolerant circuits in flash path

B Georgescu, C Zonte, V Raghavan - US Patent 9,595,332, 2017 - Google Patents
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path
includes a first inverter and a transistor. The transistor is coupled to the word line. The first …

Systems, methods, and apparatus for memory cells with common source lines

X Yu, V Prabhakar, IG Kouznetsov, LT Hinh… - US Patent …, 2016 - Google Patents
Abstract Systems, methods, and apparatus are disclosed for implementing memory cells
having common source lines. The methods may include receiving a first voltage at a first …

Two-bit magnetoresistive random-access memory device architecture

A Dutta, ER Evarts - US Patent 11,437,083, 2022 - Google Patents
A magnetoresistive random-access memory (MRAM) device includes a first cell selectively
connected to a first bit line and a second cell selectively connected to a second bit line. The …

High voltage architecture for non-volatile memory

BI Georgescu, GP Mosculak, V Raghavan… - US Patent …, 2017 - Google Patents
BACKGROUND Non-volatile memory devices are currently in widespread use in electronic
components that require the retention of information when electrical power is unavailable …

Integrated circuit devices for driving conductors to target voltage levels

M Piccardi, X Guo - US Patent 11,410,726, 2022 - Google Patents
Integrated circuit devices might include a controller configured to cause the integrated circuit
device to apply a first voltage level to a first conductor while applying a second voltage level …

Semiconductor device including memory using hafnium and a method of manufacturing the same

M Inoue, M Kadoshima, Y Kawashima… - US Patent …, 2021 - Google Patents
A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having
charge storage layer capable of holding charges, and a memory gate electrode formed on …

Systems, methods, and apparatus for memory cells with common source lines

X Yu, V Prabhakar, I Kouznetsov, L Hinh… - US Patent 10,192,622, 2019 - Google Patents
(57) ABSTRACT A method for operating a memory device includes the steps of providing a
first voltage to a first transistor of a first memory cell and a third transistor of a second …

High voltage architecture for non-volatile memory

BI Georgescu, GP Moscaluk, V Raghavan… - US Patent …, 2019 - Google Patents
A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a
memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a …

Systems, methods, and apparatus for memory cells with common source lines

X Yu, V Prabhakar, IG Kouznetsov, LT Hinh… - US Patent …, 2017 - Google Patents
Systems, methods, and apparatus are disclosed for imple menting memory cells having
common source lines. The methods may include receiving a first voltage at a first transistor …

Ferroelectric random-access memory on pre-patterned bottom electrode and oxidation barrier

S Sun - US Patent 10,079,240, 2018 - Google Patents
Abstract Structure and method of fabrication of F-RAM cells are described. The F-RAM cell
include ferroelectric capacitors forming over and with a pre-patterned barrier structure which …