Memory device programming technique for increased bits per cell
T Tanaka, HY Tseng, DV Nguyen… - US Patent …, 2024 - Google Patents
A memory device includes an array of memory cells and a controller configured to access
the array of memory cells. The controller is further configured to program a first number of …
the array of memory cells. The controller is further configured to program a first number of …
Runtime storage capacity reduction avoidance in sequentially-written memory devices
VVK Lakshmi, V Janarthanam - US Patent 12,026,372, 2024 - Google Patents
A system includes a memory device having a plurality of blocks. A first subset of the plurality
of blocks is configured as single-level cell (SLC) memory and a second subset of the …
of blocks is configured as single-level cell (SLC) memory and a second subset of the …