Each memory cell of a non-volatile semiconductor memory essentially consisting of a one-
transistor type memory cell comprising only of an MOSFET having a floating gate electrode …

US5467306A - Method of using source bias to increase threshold voltages and/or to correct for
over-erasure of flash eproms - Google Patents US5467306A - Method of using source bias to …

A computer System includes a computing device Such as a microcontroller and a memory
device. The memory device is illustratively a Serial device connected to the Serial port of the …

A charge pump is configured to receive an external voltage level and generate a high
voltage level, wherein the high voltage level is higher than the external voltage level. A …

A memory system includes an array of solidstate memory devices which are in
communication with and under the control of a controller module via a device bus with very …

A method of erasing, programming, and verifying a flash electrically erasable programmable
read-only memory where all cells are first erased to a high threshold voltage, preferably by …

(57) ABSTRACT A novel FLASH-based EEPROM cell, decoder, and layout scheme are
disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte …

A flash EPROM memory cell array includes a plurality of flash cells arranged as a matrix of
rows in columns of said cells. Each cell includes a single transistor. For each row of flash …

BACKGROUND EEPROM cells are nonvolatile memory cells that may be electrically
programmed, read, and erased. EEPROM cells typically include two transistors referred to …

The present invention relates to an electrically erasable programmable floating gate
memory, Such as flash memory or electrically erasable programmable read only memory …