Two-dimensional materials for next-generation computing technologies
Rapid digital technology advancement has resulted in a tremendous increase in computing
tasks imposing stringent energy efficiency and area efficiency requirements on next …
tasks imposing stringent energy efficiency and area efficiency requirements on next …
Spintronics for energy-efficient computing: An overview and outlook
From the discovery of giant magnetoresistance (GMR) to tunnel magnetoresistance (TMR),
their subsequent application in large capacity hard disk drives (HDDs) greatly speeded up …
their subsequent application in large capacity hard disk drives (HDDs) greatly speeded up …
In-memory computing with resistive switching devices
Modern computers are based on the von Neumann architecture in which computation and
storage are physically separated: data are fetched from the memory unit, shuttled to the …
storage are physically separated: data are fetched from the memory unit, shuttled to the …
Prime: A novel processing-in-memory architecture for neural network computation in reram-based main memory
Processing-in-memory (PIM) is a promising solution to address the" memory wall"
challenges for future computer systems. Prior proposed PIM architectures put additional …
challenges for future computer systems. Prior proposed PIM architectures put additional …
Tetris: Scalable and efficient neural network acceleration with 3d memory
The high accuracy of deep neural networks (NNs) has led to the development of NN
accelerators that improve performance by two orders of magnitude. However, scaling these …
accelerators that improve performance by two orders of magnitude. However, scaling these …
Drisa: A dram-based reconfigurable in-situ accelerator
Data movement between the processing units and the memory in traditional von Neumann
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …
architecture is creating the" memory wall" problem. To bridge the gap, two approaches, the …
25.4 a 20nm 6gb function-in-memory dram, based on hbm2 with a 1.2 tflops programmable computing unit using bank-level parallelism, for machine learning …
YC Kwon, SH Lee, J Lee, SH Kwon… - … Solid-State Circuits …, 2021 - ieeexplore.ieee.org
In recent years, artificial intelligence (AI) technology has proliferated rapidly and widely into
application areas such as speech recognition, health care, and autonomous driving. To …
application areas such as speech recognition, health care, and autonomous driving. To …
Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology
X Zou, S Xu, X Chen, L Yan, Y Han - Science China Information Sciences, 2021 - Springer
The “memory wall” problem or so-called von Neumann bottleneck limits the efficiency of
conventional computer architectures, which move data from memory to CPU for …
conventional computer architectures, which move data from memory to CPU for …
SIMDRAM: A framework for bit-serial SIMD processing using DRAM
N Hajinazar, GF Oliveira, S Gregorio… - Proceedings of the 26th …, 2021 - dl.acm.org
Processing-using-DRAM has been proposed for a limited set of basic operations (ie, logic
operations, addition). However, in order to enable full adoption of processing-using-DRAM …
operations, addition). However, in order to enable full adoption of processing-using-DRAM …
Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory
This paper presents a programmable and scalable digital neuromorphic architecture based
on 3D high-density memory integrated with logic tier for efficient neural computing. The …
on 3D high-density memory integrated with logic tier for efficient neural computing. The …