An overview of the development of a GPU with integrated HBM on silicon interposer
CC Lee, CP Hung, C Cheung, PF Yang… - 2016 IEEE 66th …, 2016 - ieeexplore.ieee.org
In recent years, the 2.5 D IC (Integrated Circuit) package with TSV (Through Silicon Vias)
has become important for high-bandwidth and high-performance applications. It is well …
has become important for high-bandwidth and high-performance applications. It is well …
[图书][B] Metrology and Diagnostic Techniques for Nanoelectronics
Z Ma, DG Seiler - 2017 - taylorfrancis.com
Nanoelectronics is changing the way the world communicates, and is transforming our daily
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …
Prediction of deformation during manufacturing processes of silicon interposer package with TSVs
The purpose of this paper is to analyze and predict the thermal deformation of the through
silicon via (TSV) interposer package during the manufacturing process and to perform a …
silicon via (TSV) interposer package during the manufacturing process and to perform a …
Chip–Package Interaction and Reliability Improvement by Structure Optimization for Ultralow- Interconnects in Flip-Chip Packages
Mechanical failures in low-k interlayer dielectrics and related interfaces during flip-chip-
packaging processes have raised serious reliability concerns. The problem can be traced to …
packaging processes have raised serious reliability concerns. The problem can be traced to …
Study of chip–package interaction parameters on interlayer dielectric crack propagation
S Raghavan, I Schmadlak, G Leal… - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
To meet the electrical performance requirements, copper traces with ultralow-k (ULK)
interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric …
interlayer dielectric (ILD) materials are used in today's semiconductor devices. The dielectric …
[HTML][HTML] An Investigation on the Most Likely Failure Locations in the BEoL Stack of a 20 nm Chip Due to Chip Package Interaction with the Use of Novel Semi-Elliptical …
G Li, Y Shi, AAO Tay, Z Long - Micromachines, 2023 - mdpi.com
The era of 20 nm integrated circuits has arrived. There exist abundant heterogeneous
micro/nano structures, with thicknesses ranging from hundreds of nanometers to sub …
micro/nano structures, with thicknesses ranging from hundreds of nanometers to sub …
The stress analysis and parametric studies for the low-k layers of a chip in the flip-chip process
L Lin, J Wang, L Wang, W Zhang - Microelectronics Reliability, 2016 - Elsevier
Using low-k/ultralow-k (LK/ULK) materials as the inter-layer dielectrics (ILD) and inter-metal
dielectrics (IMD) in copper connections were implemented to meet the electrical …
dielectrics (IMD) in copper connections were implemented to meet the electrical …
Chip‐Packaging Interaction and Reliability Impact on Cu/Low k Interconnects
G Wang, X Zhang, PS Ho - AIP Conference Proceedings, 2006 - pubs.aip.org
The packaging process can increase the driving force for interfacial delamination and
significantly impacts the reliability of the low k chip. In this study we investigated the …
significantly impacts the reliability of the low k chip. In this study we investigated the …
Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology
K Sakuma, K Smith, K Tunga, E Perfecto… - 2012 IEEE 62nd …, 2012 - ieeexplore.ieee.org
A differential heating/cooling chip join method was developed for Pb-free flip chip packaging
of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package …
of ultra low-k (ULK) technology Si chips on organic substrates to prevent Chip-Package …
Design guideline on board-level thermomechanical reliability of 2.5 D package
A vast range of electronics products have utilized 2.5 D packages for better performance and
miniaturization. As multi-level assembly technologies are getting mature, 2.5 D packaging …
miniaturization. As multi-level assembly technologies are getting mature, 2.5 D packaging …