EDEN: Enabling energy-efficient, high-performance deep neural network inference using approximate DRAM
The effectiveness of deep neural networks (DNN) in vision, speech, and language
processing has prompted a tremendous demand for energy-efficient high-performance DNN …
processing has prompted a tremendous demand for energy-efficient high-performance DNN …
The reach profiler (reaper) enabling the mitigation of dram retention failures via profiling at aggressive conditions
Modern DRAM-based systems suffer from significant energy and latency penalties due to
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability
DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …
trends in multi-core system design and large-dataset applications have amplified the role of …
Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …
Understanding and modeling on-die error correction in modern DRAM: An experimental study using real devices
Experimental characterization of DRAM errors is a powerful technique for understanding
DRAM behavior and provides valuable insights for improving overall system performance …
DRAM behavior and provides valuable insights for improving overall system performance …
A case for self-managing dram chips: Improving performance, efficiency, reliability, and security via autonomous in-dram maintenance operations
The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …
Approximate computing with partially unreliable dynamic random access memory-approximate DRAM
In the context of approximate computing, Approximate Dynamic Random Access Memory
(ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The …
(ADRAM) enables the tradeoff between energy efficiency, performance and reliability. The …
Seams: Self-optimizing runtime manager for approximate memory hierarchies
Memory approximation techniques are commonly limited in scope, targeting individual
levels of the memory hierarchy. Existing approximation techniques for a full memory …
levels of the memory hierarchy. Existing approximation techniques for a full memory …
Harmony: Heterogeneous-reliability memory and qos-aware energy management on virtualized servers
K Tovletoglou, L Mukhanov, DS Nikolopoulos… - Proceedings of the …, 2020 - dl.acm.org
The explosive growth of data increases the storage needs, especially within servers, making
DRAM responsible for more than 40% of the total system power. Such a reality has made …
DRAM responsible for more than 40% of the total system power. Such a reality has made …