The DRAM latency PUF: Quickly evaluating physical unclonable functions by exploiting the latency-reliability tradeoff in modern commodity DRAM devices
Physically Unclonable Functions (PUFs) are commonly used in cryptography to identify
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
devices based on the uniqueness of their physical microstructures. DRAM-based PUFs have …
Understanding latency variation in modern DRAM chips: Experimental characterization, analysis, and optimization
Long DRAM latency is a critical performance bottleneck in current systems. DRAM access
latency is defined by three fundamental operations that take place within the DRAM cell …
latency is defined by three fundamental operations that take place within the DRAM cell …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
Adaptive-latency DRAM: Optimizing DRAM timing for the common-case
In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
ChargeCache: Reducing DRAM latency by exploiting row access locality
DRAM latency continues to be a critical bottleneck for system performance. In this work, we
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …
What your DRAM power models are not telling you: Lessons from a detailed experimental study
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …
today, due to the increasing demand for memory capacity and bandwidth. There is a …
Design-induced latency variation in modern DRAM chips: Characterization, analysis, and latency reduction mechanisms
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work
has studied and exploited several forms of variation, such as manufacturing-process-or …
has studied and exploited several forms of variation, such as manufacturing-process-or …
SoftMC: A flexible and practical open-source infrastructure for enabling experimental DRAM studies
DRAM is the primary technology used for main memory in modern systems. Unfortunately,
as DRAM scales down to smaller technology nodes, it faces key challenges in both data …
as DRAM scales down to smaller technology nodes, it faces key challenges in both data …
Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …