Td-nuca: runtime driven management of nuca caches in task dataflow programming models

P Caheny, L Alvarez, M Casas… - … Conference for High …, 2022 - ieeexplore.ieee.org
In high performance processors, the design of on-chip memory hierarchies is crucial for
performance and energy efficiency. Current processors rely on large shared Non-Uniform …

New Efficient Approach to Solve Big Data Systems Using Parallel Gauss–Seidel Algorithms

SY Chang, HC Wu, Y Wang - Big Data and Cognitive Computing, 2022 - mdpi.com
In order to perform big-data analytics, regression involving large matrices is often necessary.
In particular, large scale regression problems are encountered when one wishes to extract …

Novel techniques to improve the performance and the energy of vector architectures

A Barredo Ferreira - 2021 - upcommons.upc.edu
The rate of annual data generation grows exponentially. At the same time, there is a high
demand to analyze that information quickly. In the past, every processor generation came …

A Fault-Tolerant Distributed Framework for Asynchronous Iterative Computations

T Zhou, L Gao, X Guan - IEEE Transactions on Parallel and …, 2021 - ieeexplore.ieee.org
Asynchronous iterative computations (AIC) are common in machine learning and data
mining systems. However, the lack of synchronization barriers in asynchronous processing …

Exploiting data locality in cache-coherent NUMA systems

I Sánchez Barrera - 2022 - upcommons.upc.edu
The end of Dennard scaling has caused a stagnation of the clock frequency in computers.
To overcome this issue, in the last two decades vendors have been integrating larger …

Exploiting task-based programming models for resilience

L Jaulmes - 2019 - upcommons.upc.edu
Hardware errors become more common as silicon technologies shrink and become more
vulnerable, especially in memory cells, which are the most exposed to errors. Permanent …

Runtime-assisted optimizations in the on-chip memory hierarchy

V Dimić - 2020 - upcommons.upc.edu
Following Moore's Law, the number of transistors on chip has been increasing
exponentially, which has led to the increasing complexity of modern processors. As a result …

Runtime-assisted coherent caching

P Caheny - 2020 - upcommons.upc.edu
In the middle of the 2000s a fundamental change of course occurred in computer
architecture because techniques such as frequency scaling and instruction level parallelism …